A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI

Journal Article · 16 October 2017 · IEEE Journal of Solid-State Circuits

DOI: https://doi.org/10.1109/jssc.2017.2749425 · OSTI ID:1427512

Chen, Man-Chia  ^[1]; Perez, Aldo Pena ^[2]; Kothapalli, Sri-Rajasekhar ^[3]; Cathelin, Philippe ^[4]; Cathelin, Andreia ^[4]; Gambhir, Sanjiv Sam ^[5]; Murmann, Boris ^[6]

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1. Robert-Bosch Sensortec, Palo Alto, CA (United States)
2. SLAC National Accelerator Lab., Menlo Park, CA (United States)
3. Pennsylvania State Univ., University Park, PA (United States)
4. STMicroelectronics, Crolles (France)
5. Stanford Univ., CA (United States). Rad/Molecular Imaging Program
6. Stanford Univ., CA (United States). Dept. of Electrical Engineering

This study presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 μm by 250 μm. The proof-of-concept receiver was implemented in an STMicroelectronics's 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a 4 × 4 subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables an efficient in-pixel A/D conversion. The per-pixel switched-capacitor ΔΣ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator's measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. Finally, the functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array.

• Research Organization: SLAC National Accelerator Laboratory (SLAC), Menlo Park, CA (United States); Stanford Univ., CA (United States); Pennsylvania State Univ., University Park, PA (United States)
• Sponsoring Organization: USDOE; National Inst. of Health (NIH) (United States); Stanford Univ. (United States); Semiconductor Research Corporation (SRC) (United States)
• Grant/Contract Number: AC02-76SF00515; NIBIB-K99EB017729
• OSTI ID: 1427512
• Journal Information: IEEE Journal of Solid-State Circuits, Vol. 52, Issue 11; ISSN 0018-9200
• Publisher: IEEECopyright Statement
• Country of Publication: United States
• Language: English