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Title: Optimization on fixed low latency implementation of the GBT core in FPGA

We present that in the upgrade of ATLAS experiment, the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system is used to interface the front end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lowermore » fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. Finally, the system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.« less
Authors:
 [1] ;  [1] ;  [1] ;  [1] ;  [1]
  1. Brookhaven National Lab. (BNL), Upton, NY (United States)
Publication Date:
Report Number(s):
BNL-200039-2018-JAAM
Journal ID: ISSN 1748-0221; TRN: US1801975
Grant/Contract Number:
SC0012704
Type:
Accepted Manuscript
Journal Name:
Journal of Instrumentation
Additional Journal Information:
Journal Volume: 12; Journal Issue: 07; Journal ID: ISSN 1748-0221
Publisher:
Institute of Physics (IOP)
Research Org:
Brookhaven National Laboratory (BNL), Upton, NY (United States)
Sponsoring Org:
USDOE Office of Science (SC), High Energy Physics (HEP) (SC-25)
Country of Publication:
United States
Language:
English
Subject:
47 OTHER INSTRUMENTATION; Fixed low latency transmission; GBT link; Transceiver in FPGA
OSTI Identifier:
1424952

Chen, K., Chen, H., Wu, W., Xu, H., and Yao, L.. Optimization on fixed low latency implementation of the GBT core in FPGA. United States: N. p., Web. doi:10.1088/1748-0221/12/07/P07011.
Chen, K., Chen, H., Wu, W., Xu, H., & Yao, L.. Optimization on fixed low latency implementation of the GBT core in FPGA. United States. doi:10.1088/1748-0221/12/07/P07011.
Chen, K., Chen, H., Wu, W., Xu, H., and Yao, L.. 2017. "Optimization on fixed low latency implementation of the GBT core in FPGA". United States. doi:10.1088/1748-0221/12/07/P07011. https://www.osti.gov/servlets/purl/1424952.
@article{osti_1424952,
title = {Optimization on fixed low latency implementation of the GBT core in FPGA},
author = {Chen, K. and Chen, H. and Wu, W. and Xu, H. and Yao, L.},
abstractNote = {We present that in the upgrade of ATLAS experiment, the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system is used to interface the front end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. Finally, the system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.},
doi = {10.1088/1748-0221/12/07/P07011},
journal = {Journal of Instrumentation},
number = 07,
volume = 12,
place = {United States},
year = {2017},
month = {7}
}