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Title: The fundamental downscaling limit of field effect transistors

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. Our findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Furthermore, different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increase in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.
Authors:
 [1] ;  [1]
  1. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Publication Date:
Report Number(s):
SAND2015-2229J
Journal ID: ISSN 0003-6951; APPLAB
Grant/Contract Number:
AC04-94AL85000
Type:
Published Article
Journal Name:
Applied Physics Letters
Additional Journal Information:
Journal Volume: 106; Journal Issue: 19; Journal ID: ISSN 0003-6951
Publisher:
American Institute of Physics (AIP)
Research Org:
Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States); Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org:
USDOE National Nuclear Security Administration (NNSA)
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING; metal insulator semiconductor structures; capacitance; dielectric devices; quantum transport; dielectrics
OSTI Identifier:
1179740
Alternate Identifier(s):
OSTI ID: 1214578; OSTI ID: 1235268