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CMOS-compatible high-voltage integrated circuits

Thesis/Dissertation:

Abstract

Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5-{mu}m CMOS process are first studied. High-voltage n- and p-channel transistors with breakdown voltages of 50 and 190 V, respectively, were fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed, and their accuracy verified by comparison with experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices. A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS-bipolar concept, is proposed and implemented. In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed.
Authors:
Publication Date:
Jan 01, 1988
Product Type:
Thesis/Dissertation
Reference Number:
EDB-90-064498
Resource Relation:
Other Information: Thesis (Ph. D.)
Subject:
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; INTEGRATED CIRCUITS; FABRICATION; MOS TRANSISTORS; BREAKDOWN; COMPATIBILITY; FUNCTIONAL MODELS; PERFORMANCE; ELECTRONIC CIRCUITS; MICROELECTRONIC CIRCUITS; SEMICONDUCTOR DEVICES; TRANSISTORS; 990200* - Mathematics & Computers
OSTI ID:
7055199
Research Organizations:
Toronto Univ., ON (Canada)
Country of Origin:
Canada
Language:
English
Availability:
National Library of Canada, Ottawa
Submitting Site:
JMT
Size:
Pages: (vp.)
Announcement Date:

Thesis/Dissertation:

Citation Formats

Parpia, Z. CMOS-compatible high-voltage integrated circuits. Canada: N. p., 1988. Web.
Parpia, Z. CMOS-compatible high-voltage integrated circuits. Canada.
Parpia, Z. 1988. "CMOS-compatible high-voltage integrated circuits." Canada.
@misc{etde_7055199,
title = {CMOS-compatible high-voltage integrated circuits}
author = {Parpia, Z}
abstractNote = {Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5-{mu}m CMOS process are first studied. High-voltage n- and p-channel transistors with breakdown voltages of 50 and 190 V, respectively, were fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed, and their accuracy verified by comparison with experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices. A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS-bipolar concept, is proposed and implemented. In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed.}
place = {Canada}
year = {1988}
month = {Jan}
}