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Solution of equations of electric power networks in multiprocessor computers; Solucao de equacoes de redes de energia eletrica em computadores multiprocessadores

Abstract

This thesis describes a methodology for decomposing the repeat solution process the equation Ax = b independent tasks to be done in parallel, based on the matrix inverse factors (W-matrix) with partitions. The partitioning scheme proposed in this thesis consists of breaking up the W-matrix according the depths of the factorization path tree. In this scheme, all the information needed to generate the partitions can be obtained straightforward from the network factorization path tree. The partitioning algorithm is simple and ease to implement. The elements of W, matrices, except the last partition, can be obtained directly from L-matrix elements, not requiring extra work. The proposed scheme guarantees that additional fills be only created in the last partition. The forward and backward solutions are performed by rows, and the strategy proposed is to schedule on beach processor the operations corresponding to a row of each partition. It should be kept in mind that the multiprocessor environments are equipped with powerful unit processor and then it seems a sound strategy to perform the multi-add elementary operations inside the hardware in order to exploit its computing efficiency. This strategy seeks to match the parallel algorithm to the parallel architecture. The precedent relations -  More>>
Publication Date:
May 01, 1991
Product Type:
Miscellaneous
Reference Number:
SCA: 240200; PA: BR-95:000081; EDB-95:155166; SN: 95001478295
Resource Relation:
Other Information: TH: Tese (Ph.D.); PBD: May 1991
Subject:
24 POWER TRANSMISSION AND DISTRIBUTION; POWER SYSTEMS; PARALLEL PROCESSING; MATRICES; ARRAY PROCESSORS; ON-LINE CONTROL SYSTEMS; PERFORMANCE; ALGORITHMS; STABILITY; REAL TIME SYSTEMS; EQUATIONS; ELECTRIC POWER; MATHEMATICS; FACTORIZATION; COMPUTER ARCHITECTURE
OSTI ID:
128535
Research Organizations:
Universidade Estadual de Campinas, SP (Brazil). Faculdade de Engenharia Eletrica
Country of Origin:
Brazil
Language:
Portugese
Other Identifying Numbers:
TRN: BR9500081
Availability:
Available from the Nuclear Information Center of CNEN, Rio de Janeiro, Brazil
Submitting Site:
BR
Size:
132 p.
Announcement Date:
Dec 07, 1995

Citation Formats

Feltrin, Antonio Padilha. Solution of equations of electric power networks in multiprocessor computers; Solucao de equacoes de redes de energia eletrica em computadores multiprocessadores. Brazil: N. p., 1991. Web.
Feltrin, Antonio Padilha. Solution of equations of electric power networks in multiprocessor computers; Solucao de equacoes de redes de energia eletrica em computadores multiprocessadores. Brazil.
Feltrin, Antonio Padilha. 1991. "Solution of equations of electric power networks in multiprocessor computers; Solucao de equacoes de redes de energia eletrica em computadores multiprocessadores." Brazil.
@misc{etde_128535,
title = {Solution of equations of electric power networks in multiprocessor computers; Solucao de equacoes de redes de energia eletrica em computadores multiprocessadores}
author = {Feltrin, Antonio Padilha}
abstractNote = {This thesis describes a methodology for decomposing the repeat solution process the equation Ax = b independent tasks to be done in parallel, based on the matrix inverse factors (W-matrix) with partitions. The partitioning scheme proposed in this thesis consists of breaking up the W-matrix according the depths of the factorization path tree. In this scheme, all the information needed to generate the partitions can be obtained straightforward from the network factorization path tree. The partitioning algorithm is simple and ease to implement. The elements of W, matrices, except the last partition, can be obtained directly from L-matrix elements, not requiring extra work. The proposed scheme guarantees that additional fills be only created in the last partition. The forward and backward solutions are performed by rows, and the strategy proposed is to schedule on beach processor the operations corresponding to a row of each partition. It should be kept in mind that the multiprocessor environments are equipped with powerful unit processor and then it seems a sound strategy to perform the multi-add elementary operations inside the hardware in order to exploit its computing efficiency. This strategy seeks to match the parallel algorithm to the parallel architecture. The precedent relations - that give rise to delays - are replaced by multi-add operations performed inside the processor mode without external communication. In the partition, the forward, diagonal and backward solutions may be gathered, and so all the operations can be expressed as the product of matrix W{sub lp} by the update components of vector b. The performance results show that the potential speedup of the solution time is essentially bounded by the floating point operation capability of each processor, denoting that the methodology is a suitable way to exploit the growing power of the computing technology. 46 figs, 40 refs, 49 tabs.}
place = {Brazil}
year = {1991}
month = {May}
}