Abstract
Four hardware simulation models implementing the FASTBUS protocol are described. The models are written in the VHDL hardware description language to obtain portability, i.e. without relations to any specific simulator. They include two complete FASTBUS devices, a full-duplex segment interconnect and ancillary logic for the segment. In addition, master and slave models using a high level interface to describe FASTBUS operations, are presented. With these models different configurations of FASTBUS systems can be evaluated and the FASTBUS transactions of new devices can be verified. (au).
Citation Formats
Appelquist, G.
FASTBUS simulation models in VHDL.
Sweden: N. p.,
1992.
Web.
Appelquist, G.
FASTBUS simulation models in VHDL.
Sweden.
Appelquist, G.
1992.
"FASTBUS simulation models in VHDL."
Sweden.
@misc{etde_10145343,
title = {FASTBUS simulation models in VHDL}
author = {Appelquist, G}
abstractNote = {Four hardware simulation models implementing the FASTBUS protocol are described. The models are written in the VHDL hardware description language to obtain portability, i.e. without relations to any specific simulator. They include two complete FASTBUS devices, a full-duplex segment interconnect and ancillary logic for the segment. In addition, master and slave models using a high level interface to describe FASTBUS operations, are presented. With these models different configurations of FASTBUS systems can be evaluated and the FASTBUS transactions of new devices can be verified. (au).}
place = {Sweden}
year = {1992}
month = {Nov}
}
title = {FASTBUS simulation models in VHDL}
author = {Appelquist, G}
abstractNote = {Four hardware simulation models implementing the FASTBUS protocol are described. The models are written in the VHDL hardware description language to obtain portability, i.e. without relations to any specific simulator. They include two complete FASTBUS devices, a full-duplex segment interconnect and ancillary logic for the segment. In addition, master and slave models using a high level interface to describe FASTBUS operations, are presented. With these models different configurations of FASTBUS systems can be evaluated and the FASTBUS transactions of new devices can be verified. (au).}
place = {Sweden}
year = {1992}
month = {Nov}
}