You need JavaScript to view this

Building a Verilog model for Boundary-Scan architecture

Abstract

This report presents a short introduction of the Boundary-Scan technique, as well as a model designed by Verilog HDL to implement the Boundary-Scan architecture. The idea of Boundary-Scan architecture provides a non-contact method of accessing chip pins during testing. The model implemented by Verilog is simple, but expresses the spirit of the standard very well. As this model is compatible with the IEEE 1149.1 standard it provides the possibility of implementing it in the real world. 11 refs., 11 figs., 2 tabs.
Authors:
Publication Date:
Dec 01, 1992
Product Type:
Technical Report
Report Number:
OUP-92-40
Reference Number:
SCA: 440101; PA: AIX-24:039178; SN: 93000980119
Resource Relation:
Other Information: PBD: Dec 1992
Subject:
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY; DIGITAL SYSTEMS; PERFORMANCE TESTING; NUCLEAR INSTRUMENT MODULES; COMPUTER ARCHITECTURE; ANALOG-TO-DIGITAL CONVERTERS; ELECTRICAL TESTING; EQUIPMENT INTERFACES; OSLO CYCLOTRON; 440101; GENERAL DETECTORS OR MONITORS AND RADIOMETRIC INSTRUMENTS
OSTI ID:
10145296
Research Organizations:
Oslo Univ. (Norway). Fysisk Inst.
Country of Origin:
Norway
Language:
English
Other Identifying Numbers:
Journal ID: ISSN 0332-5571; Other: ON: DE93623878; TRN: NO9300001039178
Availability:
OSTI; NTIS; INIS
Submitting Site:
NWN
Size:
[19] p.
Announcement Date:
Jul 05, 2005

Citation Formats

Wu, B, and Midttun, G. Building a Verilog model for Boundary-Scan architecture. Norway: N. p., 1992. Web.
Wu, B, & Midttun, G. Building a Verilog model for Boundary-Scan architecture. Norway.
Wu, B, and Midttun, G. 1992. "Building a Verilog model for Boundary-Scan architecture." Norway.
@misc{etde_10145296,
title = {Building a Verilog model for Boundary-Scan architecture}
author = {Wu, B, and Midttun, G}
abstractNote = {This report presents a short introduction of the Boundary-Scan technique, as well as a model designed by Verilog HDL to implement the Boundary-Scan architecture. The idea of Boundary-Scan architecture provides a non-contact method of accessing chip pins during testing. The model implemented by Verilog is simple, but expresses the spirit of the standard very well. As this model is compatible with the IEEE 1149.1 standard it provides the possibility of implementing it in the real world. 11 refs., 11 figs., 2 tabs.}
place = {Norway}
year = {1992}
month = {Dec}
}