Abstract
The specifications and implementation details of CAMAC Crate Controller CC-3 for IBM-PC compatible as a host computer, having capability to transfer high speed data with direct memory access (DMA) scheme and logic to execute CAMAC cycles directly from the crate controller, to implement the block algorithms specified in ANSI/IEEE Std. 683-1976 (Reaff-1981) are described. The maximum data transfer rate measured with 8 bit interface of PC-AT is 240K byte per second. This work is carried out under Seventh Five Year Plan Project on Modernisation of reactor Control Instrumentation and Development of CAMAC and Fastbus Instrumentation. (author). 9 refs., 5 figs., 4 appendixes.
Khare, A N;
Ghodgaonkar, M D;
Bairi, B R
[1]
- Bhabha Atomic Research Centre, Bombay (India). Electronics Div.
Citation Formats
Khare, A N, Ghodgaonkar, M D, and Bairi, B R.
CC-3 CAMAC crate controller for IBM PC.
India: N. p.,
1991.
Web.
Khare, A N, Ghodgaonkar, M D, & Bairi, B R.
CC-3 CAMAC crate controller for IBM PC.
India.
Khare, A N, Ghodgaonkar, M D, and Bairi, B R.
1991.
"CC-3 CAMAC crate controller for IBM PC."
India.
@misc{etde_10128413,
title = {CC-3 CAMAC crate controller for IBM PC}
author = {Khare, A N, Ghodgaonkar, M D, and Bairi, B R}
abstractNote = {The specifications and implementation details of CAMAC Crate Controller CC-3 for IBM-PC compatible as a host computer, having capability to transfer high speed data with direct memory access (DMA) scheme and logic to execute CAMAC cycles directly from the crate controller, to implement the block algorithms specified in ANSI/IEEE Std. 683-1976 (Reaff-1981) are described. The maximum data transfer rate measured with 8 bit interface of PC-AT is 240K byte per second. This work is carried out under Seventh Five Year Plan Project on Modernisation of reactor Control Instrumentation and Development of CAMAC and Fastbus Instrumentation. (author). 9 refs., 5 figs., 4 appendixes.}
place = {India}
year = {1991}
month = {Dec}
}
title = {CC-3 CAMAC crate controller for IBM PC}
author = {Khare, A N, Ghodgaonkar, M D, and Bairi, B R}
abstractNote = {The specifications and implementation details of CAMAC Crate Controller CC-3 for IBM-PC compatible as a host computer, having capability to transfer high speed data with direct memory access (DMA) scheme and logic to execute CAMAC cycles directly from the crate controller, to implement the block algorithms specified in ANSI/IEEE Std. 683-1976 (Reaff-1981) are described. The maximum data transfer rate measured with 8 bit interface of PC-AT is 240K byte per second. This work is carried out under Seventh Five Year Plan Project on Modernisation of reactor Control Instrumentation and Development of CAMAC and Fastbus Instrumentation. (author). 9 refs., 5 figs., 4 appendixes.}
place = {India}
year = {1991}
month = {Dec}
}