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Dual port memory 256 Kb/1 Mb at rate up to 10 Mb/s; Dvukhportovaya pamyat` 256 Kbajt/1 Mbajt s bystrodejstviem do 10 Mbajt/s

Technical Report:

Abstract

A CAMAC memory module based on DRAMs 64K=1 (or 256K=1) has been developed. It allows data transfer both via the rear panel and front panel in 8 or 16 words at rates up to 10 MD/s from arbitrary address with autoincrementation. Modules may be concatenated by a daisy-chain connection. 7 refs.
Publication Date:
Dec 31, 1990
Product Type:
Technical Report
Report Number:
IFVE-OEF-90-104
Reference Number:
SCA: 990200; PA: AIX-23:017449; SN: 92000661297
Resource Relation:
Other Information: PBD: 1990
Subject:
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; MEMORY DEVICES; DATA TRANSMISSION; CAMAC SYSTEM; FLOWSHEETS; 990200; MATHEMATICS AND COMPUTERS
OSTI ID:
10118309
Research Organizations:
Gosudarstvennyj Komitet po Ispol`zovaniyu Atomnoj Ehnergii SSSR, Serpukhov (Russian Federation). Inst. Fiziki Vysokikh Ehnergij
Country of Origin:
USSR
Language:
Russian
Other Identifying Numbers:
Other: ON: DE92616800; TRN: SU9109392017449
Availability:
OSTI; NTIS (US Sales Only); INIS
Submitting Site:
INIS
Size:
6 p.
Announcement Date:
Jun 30, 2005

Technical Report:

Citation Formats

Golovkin, S V, Golubev, V V, Kozarenko, E N, and Shejnin, A B. Dual port memory 256 Kb/1 Mb at rate up to 10 Mb/s; Dvukhportovaya pamyat` 256 Kbajt/1 Mbajt s bystrodejstviem do 10 Mbajt/s. USSR: N. p., 1990. Web.
Golovkin, S V, Golubev, V V, Kozarenko, E N, & Shejnin, A B. Dual port memory 256 Kb/1 Mb at rate up to 10 Mb/s; Dvukhportovaya pamyat` 256 Kbajt/1 Mbajt s bystrodejstviem do 10 Mbajt/s. USSR.
Golovkin, S V, Golubev, V V, Kozarenko, E N, and Shejnin, A B. 1990. "Dual port memory 256 Kb/1 Mb at rate up to 10 Mb/s; Dvukhportovaya pamyat` 256 Kbajt/1 Mbajt s bystrodejstviem do 10 Mbajt/s." USSR.
@misc{etde_10118309,
title = {Dual port memory 256 Kb/1 Mb at rate up to 10 Mb/s; Dvukhportovaya pamyat` 256 Kbajt/1 Mbajt s bystrodejstviem do 10 Mbajt/s}
author = {Golovkin, S V, Golubev, V V, Kozarenko, E N, and Shejnin, A B}
abstractNote = {A CAMAC memory module based on DRAMs 64K=1 (or 256K=1) has been developed. It allows data transfer both via the rear panel and front panel in 8 or 16 words at rates up to 10 MD/s from arbitrary address with autoincrementation. Modules may be concatenated by a daisy-chain connection. 7 refs.}
place = {USSR}
year = {1990}
month = {Dec}
}