L-connect routing of die surface pads to the die edge for stacking in a 3D array
Abstract
Integrated circuit chips and method of routing the interface pads from the face of the chip or die to one or more sidewall surfaces of the die. The interconnection is routed from the face of the die to one or more edges of the die, then routed over the edge of the die and onto the side surface. A new pad is then formed on the sidewall surface, which allows multiple die or chips to be stacked in a three-dimensional array, while enabling follow-on signal routing from the sidewall pads. The routing of the interconnects and formation of the sidewall pads can be carried out in an L-connect or L-shaped routing configuration, using a metalization process such as laser pantography.
- Inventors:
-
- Dublin, CA
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- OSTI Identifier:
- 872896
- Patent Number(s):
- 6034438
- Assignee:
- Regents of University of California (Oakland, CA)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
- DOE Contract Number:
- W-7405-ENG-48
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- l-connect; routing; die; surface; pads; edge; stacking; 3d; array; integrated; circuit; chips; method; interface; chip; sidewall; surfaces; interconnection; routed; edges; pad; formed; allows; multiple; stacked; three-dimensional; enabling; follow-on; signal; interconnects; formation; carried; l-shaped; configuration; metalization; process; laser; pantography; wall surface; integrated circuit; wall surfaces; circuit chip; circuit chips; laser pantography; interface pads; dimensional array; laser pantograph; /257/
Citation Formats
Petersen, Robert W. L-connect routing of die surface pads to the die edge for stacking in a 3D array. United States: N. p., 2000.
Web.
Petersen, Robert W. L-connect routing of die surface pads to the die edge for stacking in a 3D array. United States.
Petersen, Robert W. Sat .
"L-connect routing of die surface pads to the die edge for stacking in a 3D array". United States. https://www.osti.gov/servlets/purl/872896.
@article{osti_872896,
title = {L-connect routing of die surface pads to the die edge for stacking in a 3D array},
author = {Petersen, Robert W},
abstractNote = {Integrated circuit chips and method of routing the interface pads from the face of the chip or die to one or more sidewall surfaces of the die. The interconnection is routed from the face of the die to one or more edges of the die, then routed over the edge of the die and onto the side surface. A new pad is then formed on the sidewall surface, which allows multiple die or chips to be stacked in a three-dimensional array, while enabling follow-on signal routing from the sidewall pads. The routing of the interconnects and formation of the sidewall pads can be carried out in an L-connect or L-shaped routing configuration, using a metalization process such as laser pantography.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Sat Jan 01 00:00:00 EST 2000},
month = {Sat Jan 01 00:00:00 EST 2000}
}
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