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Title: Methods of fabricating applique circuits

Abstract

Applique circuits suitable for advanced packaging applications are introduced. These structures are particularly suited for the simple integration of large amounts (many nanoFarads) of capacitance into conventional integrated circuit and multichip packaging technology. In operation, applique circuits are bonded to the integrated circuit or other appropriate structure at the point where the capacitance is required, thereby minimizing the effects of parasitic coupling. An immediate application is to problems of noise reduction and control in modern high-frequency circuitry.

Inventors:
 [1];  [1]
  1. Albuquerque, NM
Issue Date:
Research Org.:
Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
OSTI Identifier:
872509
Patent Number(s):
5950292
Application Number:
08/811,305
Assignee:
Sandia Corporation (Albuquerque, NM)
Patent Classifications (CPCs):
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
H - ELECTRICITY H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR H05K - PRINTED CIRCUITS
DOE Contract Number:  
AC04-94DP85000
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
methods; fabricating; applique; circuits; suitable; advanced; packaging; applications; introduced; structures; particularly; suited; simple; integration; amounts; nanofarads; capacitance; conventional; integrated; circuit; multichip; technology; operation; bonded; appropriate; structure; required; minimizing; effects; parasitic; coupling; immediate; application; noise; reduction; control; modern; high-frequency; circuitry; particularly suited; integrated circuit; applique circuits; noise reduction; frequency circuit; /29/216/427/

Citation Formats

Dimos, Duane B, and Garino, Terry J. Methods of fabricating applique circuits. United States: N. p., 1999. Web.
Dimos, Duane B, & Garino, Terry J. Methods of fabricating applique circuits. United States.
Dimos, Duane B, and Garino, Terry J. Tue . "Methods of fabricating applique circuits". United States. https://www.osti.gov/servlets/purl/872509.
@article{osti_872509,
title = {Methods of fabricating applique circuits},
author = {Dimos, Duane B and Garino, Terry J},
abstractNote = {Applique circuits suitable for advanced packaging applications are introduced. These structures are particularly suited for the simple integration of large amounts (many nanoFarads) of capacitance into conventional integrated circuit and multichip packaging technology. In operation, applique circuits are bonded to the integrated circuit or other appropriate structure at the point where the capacitance is required, thereby minimizing the effects of parasitic coupling. An immediate application is to problems of noise reduction and control in modern high-frequency circuitry.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Sep 14 00:00:00 EDT 1999},
month = {Tue Sep 14 00:00:00 EDT 1999}
}

Works referenced in this record:

Integrated Decoupling Capacitors using Pb(Zr,Ti)O 3 Thin Films
journal, January 1996