Method and apparatus for high speed data acquisition and processing
Abstract
A method and apparatus for high speed digital data acquisition. The apparatus includes one or more multiplexers for receiving multiple channels of digital data at a low data rate and asserting a multiplexed data stream at a high data rate, and one or more FIFO memories for receiving data from the multiplexers and asserting the data to a real time processor. Preferably, the invention includes two multiplexers, two FIFO memories, and a 64-bit bus connecting the FIFO memories with the processor. Each multiplexer receives four channels of 14-bit digital data at a rate of up to 5 MHz per channel, and outputs a data stream to one of the FIFO memories at a rate of 20 MHz. The FIFO memories assert output data in parallel to the 64-bit bus, thus transferring 14-bit data values to the processor at a combined rate of 40 MHz. The real time processor is preferably a floating-point processor which processes 32-bit floating-point words. A set of mask bits is prestored in each 32-bit storage location of the processor memory into which a 14-bit data value is to be written. After data transfer from the FIFO memories, mask bits are concatenated with each stored 14-bit datamore »
- Inventors:
-
- San Diego, CA
- Issue Date:
- Research Org.:
- General Atomics, San Diego, CA (United States)
- OSTI Identifier:
- 870832
- Patent Number(s):
- 5602994
- Assignee:
- United States of America as represented by United States (Washington, DC)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC03-89ER51114
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- method; apparatus; speed; data; acquisition; processing; digital; multiplexers; receiving; multiple; channels; rate; asserting; multiplexed; stream; fifo; memories; time; processor; preferably; 64-bit; bus; connecting; multiplexer; receives; 14-bit; mhz; channel; outputs; 20; assert; output; parallel; transferring; values; combined; 40; floating-point; processes; 32-bit; words; set; mask; bits; prestored; storage; location; memory; value; written; transfer; concatenated; stored; define; valid; word; user; select; modes; starting; stopping; direct; transfers; setting; content; control; status; register; bit data; output data; digital data; multiple channel; data acquisition; speed data; data stream; multiple channels; data values; data rate; speed digital; data value; /710/707/711/
Citation Formats
Ferron, John R. Method and apparatus for high speed data acquisition and processing. United States: N. p., 1997.
Web.
Ferron, John R. Method and apparatus for high speed data acquisition and processing. United States.
Ferron, John R. Wed .
"Method and apparatus for high speed data acquisition and processing". United States. https://www.osti.gov/servlets/purl/870832.
@article{osti_870832,
title = {Method and apparatus for high speed data acquisition and processing},
author = {Ferron, John R},
abstractNote = {A method and apparatus for high speed digital data acquisition. The apparatus includes one or more multiplexers for receiving multiple channels of digital data at a low data rate and asserting a multiplexed data stream at a high data rate, and one or more FIFO memories for receiving data from the multiplexers and asserting the data to a real time processor. Preferably, the invention includes two multiplexers, two FIFO memories, and a 64-bit bus connecting the FIFO memories with the processor. Each multiplexer receives four channels of 14-bit digital data at a rate of up to 5 MHz per channel, and outputs a data stream to one of the FIFO memories at a rate of 20 MHz. The FIFO memories assert output data in parallel to the 64-bit bus, thus transferring 14-bit data values to the processor at a combined rate of 40 MHz. The real time processor is preferably a floating-point processor which processes 32-bit floating-point words. A set of mask bits is prestored in each 32-bit storage location of the processor memory into which a 14-bit data value is to be written. After data transfer from the FIFO memories, mask bits are concatenated with each stored 14-bit data value to define a valid 32-bit floating-point word. Preferably, a user can select any of several modes for starting and stopping direct memory transfers of data from the FIFO memories to memory within the real time processor, by setting the content of a control and status register.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Wed Jan 01 00:00:00 EST 1997},
month = {Wed Jan 01 00:00:00 EST 1997}
}
Works referenced in this record:
Real time analysis of tokamak discharge parameters
journal, October 1992
- Ferron, J. R.; Strait, E. J.
- Review of Scientific Instruments, Vol. 63, Issue 10