Reprogrammable read only variable threshold transistor memory with isolated addressing buffer
Abstract
A monolithic integrated circuit, fully decoded memory comprises a rectangular array of variable threshold field effect transistors organized into a plurality of multi-bit words. Binary address inputs to the memory are decoded by a field effect transistor decoder into a plurality of word selection lines each of which activates an address buffer circuit. Each address buffer circuit, in turn, drives a word line of the memory array. In accordance with the word line selected by the decoder the activated buffer circuit directs reading or writing voltages to the transistors comprising the memory words. All of the buffer circuits additionally are connected to a common terminal for clearing all of the memory transistors to a predetermined state by the application to the common terminal of a large magnitude voltage of a predetermined polarity. The address decoder, the buffer and the memory array, as well as control and input/output control and buffer field effect transistor circuits, are fabricated on a common substrate with means provided to isolate the substrate of the address buffer transistors from the remainder of the substrate so that the bulk clearing function of simultaneously placing all of the memory transistors into a predetermined state can be performed.
- Inventors:
-
- Tewksbury, MA
- Issue Date:
- Research Org.:
- Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
- OSTI Identifier:
- 862604
- Patent Number(s):
- 3971001
- Assignee:
- Sperry Rand Corporation (New York, NY)
- Patent Classifications (CPCs):
-
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
- DOE Contract Number:
- AT(29-1)-789
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- reprogrammable; variable; threshold; transistor; memory; isolated; addressing; buffer; monolithic; integrated; circuit; decoded; comprises; rectangular; array; field; effect; transistors; organized; plurality; multi-bit; words; binary; address; inputs; decoder; word; selection; lines; activates; drives; line; accordance; selected; activated; directs; reading; writing; voltages; comprising; circuits; additionally; connected; common; terminal; clearing; predetermined; application; magnitude; voltage; polarity; control; input; output; fabricated; substrate; means; provided; isolate; remainder; bulk; function; simultaneously; placing; performed; memory array; common substrate; common terminal; field effect; integrated circuit; effect transistor; rectangular array; means provided; monolithic integrated; memory comprises; effect transistors; variable threshold; memory transistor; /365/257/326/327/
Citation Formats
Lodi, Robert J. Reprogrammable read only variable threshold transistor memory with isolated addressing buffer. United States: N. p., 1976.
Web.
Lodi, Robert J. Reprogrammable read only variable threshold transistor memory with isolated addressing buffer. United States.
Lodi, Robert J. Thu .
"Reprogrammable read only variable threshold transistor memory with isolated addressing buffer". United States. https://www.osti.gov/servlets/purl/862604.
@article{osti_862604,
title = {Reprogrammable read only variable threshold transistor memory with isolated addressing buffer},
author = {Lodi, Robert J},
abstractNote = {A monolithic integrated circuit, fully decoded memory comprises a rectangular array of variable threshold field effect transistors organized into a plurality of multi-bit words. Binary address inputs to the memory are decoded by a field effect transistor decoder into a plurality of word selection lines each of which activates an address buffer circuit. Each address buffer circuit, in turn, drives a word line of the memory array. In accordance with the word line selected by the decoder the activated buffer circuit directs reading or writing voltages to the transistors comprising the memory words. All of the buffer circuits additionally are connected to a common terminal for clearing all of the memory transistors to a predetermined state by the application to the common terminal of a large magnitude voltage of a predetermined polarity. The address decoder, the buffer and the memory array, as well as control and input/output control and buffer field effect transistor circuits, are fabricated on a common substrate with means provided to isolate the substrate of the address buffer transistors from the remainder of the substrate so that the bulk clearing function of simultaneously placing all of the memory transistors into a predetermined state can be performed.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Thu Jan 01 00:00:00 EST 1976},
month = {Thu Jan 01 00:00:00 EST 1976}
}