Securing against errors in an error correcting code (ECC) implemented in an automotive system

Saxena, Nirmal Raj

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Title: Securing against errors in an error correcting code (ECC) implemented in an automotive system

Abstract

In general, data is susceptible to errors caused by faults in hardware (i.e. permanent faults), such as faults in the functioning of memory and/or communication channels. To detect errors in data caused by hardware faults, the error correcting code (ECC) was introduced, which essentially provides a sort of redundancy to the data that can be used to validate that the data is free from errors caused by hardware faults. In some cases, the ECC can also be used to correct errors in the data caused by hardware faults. However, the ECC itself is also susceptible to errors, including specifically errors caused by faults in the ECC logic. A method, computer readable medium, and system are thus provided for securing against errors in an ECC.

Inventors:: Saxena, Nirmal Raj

Issue Date:: Tue Feb 02 00:00:00 EST 2021

Research Org.:: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1805471

Patent Number(s):: 10908995

Application Number:: 16/137,002

Assignee:: NVIDIA Corp. (Santa Clara, CA)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/1048 - {using arrangements adapted for a specific error detection or correction feature}
G06F11/1076 - {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING
H03M13/19 - Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
H03M13/2906 - {using block codes

Show less

DOE Contract Number:: AC52-07NA27344; B620719

Resource Type:: Patent

Resource Relation:: Patent File Date: 09/20/2018

Country of Publication:: United States

Language:: English

Citation Formats


                    Saxena, Nirmal Raj. Securing against errors in an error correcting code (ECC) implemented in an automotive system.  United States: N. p., 2021. 
        Web.

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                    Saxena, Nirmal Raj. Securing against errors in an error correcting code (ECC) implemented in an automotive system.  United States.

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                    Saxena, Nirmal Raj. Tue .  
        "Securing against errors in an error correcting code (ECC) implemented in an automotive system".  United States.  https://www.osti.gov/servlets/purl/1805471.

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@article{osti_1805471,

  title        = {Securing against errors in an error correcting code (ECC) implemented in an automotive system},

  author       = {Saxena, Nirmal Raj},

  abstractNote = {In general, data is susceptible to errors caused by faults in hardware (i.e. permanent faults), such as faults in the functioning of memory and/or communication channels. To detect errors in data caused by hardware faults, the error correcting code (ECC) was introduced, which essentially provides a sort of redundancy to the data that can be used to validate that the data is free from errors caused by hardware faults. In some cases, the ECC can also be used to correct errors in the data caused by hardware faults. However, the ECC itself is also susceptible to errors, including specifically errors caused by faults in the ECC logic. A method, computer readable medium, and system are thus provided for securing against errors in an ECC.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Tue Feb 02 00:00:00 EST 2021},

  month        = {Tue Feb 02 00:00:00 EST 2021}

}

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Works referenced in this record:

Reduced-overhead error detection and correction
patent, October 2017

Ware, Frederick A.; Leibowitz, Brian S.
US Patent Document 9,785,500
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9785500

Semiconductor memory device including non-volatile memory, cache memory, and computer system
patent-application, May 2014

Kim, Sun-gyeum; Kwon, Hyeok-man; Kwon, Young-jun
US Patent Application 13/790113; 20140149827
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20140149827

Semiconductor Memory Device Having Selective ECC Function
patent-application, February 2016

Park, Jong-wook; Park, Ki-won
US Patent Application 14/636548; 20160034348
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20160034348

Method of ECC Encoding a Dram and Dram
patent-application, November 2018

Minzoni, Alesandro
US Patent Application 15/982097; 20180336959
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20180336959

Memory device check bit read mode
patent, December 2017

Halbert, John B.; Bains, Kuljit S.
US Patent Document 9,842,021
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9842021

ECC code mechanism to detect wire stuck-at faults
patent, June 2005

Sharma, Debendra Das
US Patent Document 6,910,169
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6910169

Transparent error correcting memory
patent-application, February 2005

Leung, Wingyu; Tam, Kit Sang; Tworek, Mikolaj
US Patent Application 10/645861; 20050044467
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20050044467

Latch arrangement for an electronic digital system, method, data processing program, and computer program product for implementing a latch arrangement
patent, August 2013

Cremer, Michael; Gerwig, Guenter; Lehnert, Frank
US Patent Document 8,516,336
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8516336

Implementing ECC redundancy using reconfigurable logic blocks
patent, January 2016

Cordero, Edgar R.; Dell, Timothy J.; Henderson, Joab D.
US Patent Document 9,230,687
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9230687

Systems and methods for adaptive data storage
patent-application, July 2013

Flynn, David; Strasser, John; Inskeep, Bill
US Patent Application 13/784705; 20130179753
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20130179753

Double consecutive error correction
patent, August 2017

Gendler, Alexander; Cohen, Gilad
US Patent Document 9,748,977
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9748977

Safe execution in place (XIP) from flash memory
patent, August 2019

Aberl, Peter; Dubey, Aishwarya; Sagar, Rajat
US Patent Document 10,388,392
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/10388392

Apparatus and Method for Generating an Error Code for a Block Comprising a Plurality of Data Bits and a Plurality of Address Bits
patent-application, November 2017

Johar, Kauser Yakub
US Patent Application 15/587429; 20170346504
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20170346504

Multiple processor system with standby sparing
patent, December 2002

Horst, Robert W.; Garcia, David J.
US Patent Document 6,496,940
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6496940

System and method for optimizing source code
patent, September 2011

Miranda, Miguel; Catthoor, Francky; Janssen, Martin
US Patent Document 8,024,718
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8024718

Method and apparatus for performing error correction code (ECC) conversion
patent-application, July 2004

Williams, Emrys
US Patent Application 10/337580; 20040133836
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20040133836

Apparatus for error detection in memory devices
patent, September 2016

Marshall, Ray; Circello, Joseph C.; Von Wendorff, Wilhard
US Patent Document 9,436,546
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9436546

Nonvolatile memory device including dummy wordline, memory system, and method of operating memory system
patent-application, April 2015

Jung, Bong-Kil; Byeon, Dae-Seok
US Patent Application 14/463130; 20150113342
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20150113342

Encoding and syndrome computing co-design circuit for BCH code and method for deciding the same
patent, May 2016

Hung, Jui Hui; Yen, Chih Nan
US Patent Document 9,337,869
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9337869

Safe Execution in Place (XIP) From Flash Memory
patent-application, October 2018

Aberl, Peter; Dubey, Aishwarya; Sagar, Rajat
US Patent Application 15/482729; 20180293129
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20180293129

Transparent error correcting memory
patent, April 2008

Leung, Wingyu; Tam, Kit S.; Tworek, Mikolaj
US Patent Document 7,353,438
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7353438

Validation of Memory on-Die Error Correction Mode
patent-application, October 2017

Halbert, John B.; Bains, Kuljit S.
US Patent Application 15/089316; 20170286197
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20170286197

Error code management in systems permitting partial writes
patent, July 2016

Orion, Luc
US Patent Document 9,384,091
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9384091

DRAM error detection, evaluation, and correction
patent, July 2015

Franceschini, Michele M.; Hunter, Hillery C.; Jagmohan, Ashish
US Patent Document 9,087,612
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/9087612

Low cost adjacent double error correcting code
patent, October 2014

Dutta, Avijit
US Patent Document 8,875,002
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8875002

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Title: Securing against errors in an error correcting code (ECC) implemented in an automotive system

Abstract

Citation Formats

Reduced-overhead error detection and correction patent, October 2017

Semiconductor memory device including non-volatile memory, cache memory, and computer system patent-application, May 2014

Semiconductor Memory Device Having Selective ECC Function patent-application, February 2016

Method of ECC Encoding a Dram and Dram patent-application, November 2018

Memory device check bit read mode patent, December 2017

ECC code mechanism to detect wire stuck-at faults patent, June 2005

Transparent error correcting memory patent-application, February 2005

Latch arrangement for an electronic digital system, method, data processing program, and computer program product for implementing a latch arrangement patent, August 2013

Implementing ECC redundancy using reconfigurable logic blocks patent, January 2016

Systems and methods for adaptive data storage patent-application, July 2013

Double consecutive error correction patent, August 2017

Safe execution in place (XIP) from flash memory patent, August 2019

Apparatus and Method for Generating an Error Code for a Block Comprising a Plurality of Data Bits and a Plurality of Address Bits patent-application, November 2017

Multiple processor system with standby sparing patent, December 2002

System and method for optimizing source code patent, September 2011

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Apparatus for error detection in memory devices patent, September 2016

Nonvolatile memory device including dummy wordline, memory system, and method of operating memory system patent-application, April 2015

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Low cost adjacent double error correcting code patent, October 2014

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Semiconductor memory device including non-volatile memory, cache memory, and computer system
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Semiconductor Memory Device Having Selective ECC Function
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Method of ECC Encoding a Dram and Dram
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Memory device check bit read mode
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ECC code mechanism to detect wire stuck-at faults
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Transparent error correcting memory
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Latch arrangement for an electronic digital system, method, data processing program, and computer program product for implementing a latch arrangement
patent, August 2013

Implementing ECC redundancy using reconfigurable logic blocks
patent, January 2016

Systems and methods for adaptive data storage
patent-application, July 2013

Double consecutive error correction
patent, August 2017

Safe execution in place (XIP) from flash memory
patent, August 2019

Apparatus and Method for Generating an Error Code for a Block Comprising a Plurality of Data Bits and a Plurality of Address Bits
patent-application, November 2017

Multiple processor system with standby sparing
patent, December 2002

System and method for optimizing source code
patent, September 2011

Method and apparatus for performing error correction code (ECC) conversion
patent-application, July 2004

Apparatus for error detection in memory devices
patent, September 2016

Nonvolatile memory device including dummy wordline, memory system, and method of operating memory system
patent-application, April 2015

Encoding and syndrome computing co-design circuit for BCH code and method for deciding the same
patent, May 2016

Safe Execution in Place (XIP) From Flash Memory
patent-application, October 2018

Transparent error correcting memory
patent, April 2008

Validation of Memory on-Die Error Correction Mode
patent-application, October 2017

Error code management in systems permitting partial writes
patent, July 2016

DRAM error detection, evaluation, and correction
patent, July 2015

Low cost adjacent double error correcting code
patent, October 2014