High-density latch arrays
Abstract
A system and device are provided for implementing memory arrays using high-density latch cells. The device includes an array of cells arranged into columns and rows. Each cell comprises a latch cell that includes a transmission gate, a pair of inverters, and an output buffer. Each row of latch cells is connected to at least one common node for addressing the row of latch cells, and each column of latch cells is connected to a particular bit of an input signal and a particular bit of an output signal. A register file may be implemented using one or more arrays of the high-density latch cells to replace any or all of the banks of SRAM cells typically used to implement the register file.
- Inventors:
- Issue Date:
- Research Org.:
- NVIDIA Corp., Santa Clara, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1532145
- Patent Number(s):
- 9245601
- Application Number:
- 14/296,320
- Assignee:
- NVIDIA Corporation (Santa Clara, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
- DOE Contract Number:
- B599861
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2014-06-04
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Sinangil, Mahmut Ersin, Poulton, John W., Khailany, Brucek Kurdo, and Edmondson, John H. High-density latch arrays. United States: N. p., 2016.
Web.
Sinangil, Mahmut Ersin, Poulton, John W., Khailany, Brucek Kurdo, & Edmondson, John H. High-density latch arrays. United States.
Sinangil, Mahmut Ersin, Poulton, John W., Khailany, Brucek Kurdo, and Edmondson, John H. Tue .
"High-density latch arrays". United States. https://www.osti.gov/servlets/purl/1532145.
@article{osti_1532145,
title = {High-density latch arrays},
author = {Sinangil, Mahmut Ersin and Poulton, John W. and Khailany, Brucek Kurdo and Edmondson, John H.},
abstractNote = {A system and device are provided for implementing memory arrays using high-density latch cells. The device includes an array of cells arranged into columns and rows. Each cell comprises a latch cell that includes a transmission gate, a pair of inverters, and an output buffer. Each row of latch cells is connected to at least one common node for addressing the row of latch cells, and each column of latch cells is connected to a particular bit of an input signal and a particular bit of an output signal. A register file may be implemented using one or more arrays of the high-density latch cells to replace any or all of the banks of SRAM cells typically used to implement the register file.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Jan 26 00:00:00 EST 2016},
month = {Tue Jan 26 00:00:00 EST 2016}
}
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