Multiple core computer processor with globally-accessible local memories
Abstract
A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.
- Inventors:
- Issue Date:
- Research Org.:
- Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1489513
- Patent Number(s):
- 10102179
- Application Number:
- 15/243,634
- Assignee:
- THE REGENTS OF THE UNIVERSITY OF CALIFORNIA (Oakland, CA)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
- DOE Contract Number:
- AC02-05CH11231
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2016 Aug 22
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Shalf, John, Donofrio, David, and Oliker, Leonid. Multiple core computer processor with globally-accessible local memories. United States: N. p., 2018.
Web.
Shalf, John, Donofrio, David, & Oliker, Leonid. Multiple core computer processor with globally-accessible local memories. United States.
Shalf, John, Donofrio, David, and Oliker, Leonid. Tue .
"Multiple core computer processor with globally-accessible local memories". United States. https://www.osti.gov/servlets/purl/1489513.
@article{osti_1489513,
title = {Multiple core computer processor with globally-accessible local memories},
author = {Shalf, John and Donofrio, David and Oliker, Leonid},
abstractNote = {A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Oct 16 00:00:00 EDT 2018},
month = {Tue Oct 16 00:00:00 EDT 2018}
}
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