Title: Centrally managed unified shared virtual address space

Abstract

Systems, apparatuses, and methods for managing a unified shared virtual address space. A host may execute system software and manage a plurality of nodes coupled to the host. The host may send work tasks to the nodes, and for each node, the host may externally manage the node's view of the system's virtual address space. Each node may have a central processing unit (CPU) style memory management unit (MMU) with an internal translation lookaside buffer (TLB). In one embodiment, the host may be coupled to a given node via an input/output memory management unit (IOMMU) interface, where the IOMMU frontend interface shares the TLB with the given node's MMU. In another embodiment, the host may control the given node's view of virtual address space via memory-mapped control registers.

Inventors:

Wilkes, John

Issue Date:

Tue Feb 13 00:00:00 EST 2018

Research Org.:

Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1420778

Patent Number(s):

9892058

Application Number:

14/970,940

Assignee:

Advanced Micro Devices, Inc. (Sunnyvale, CA)

Patent Classifications (CPCs):

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

G06F12/1027 - using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F12/1081 - for peripheral access to main memory, e.g. direct memory access [DMA]
G06F13/1673 - {using buffers}
G06F2212/1024 - Latency reduction
G06F2212/656 - Address space sharing
G06F2212/682 - Multiprocessor TLB consistency

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

Y02D10/00 - Energy efficient computing

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DOE Contract Number:  

AC52-07NA27344

Resource Type:

Patent

Resource Relation:

Patent File Date: 2015 Dec 16

Country of Publication:

United States

Language:

English

Subject:

97 MATHEMATICS AND COMPUTING