Wire like link for cycle reproducible and cycle accurate hardware accelerator
Abstract
First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1177498
- Patent Number(s):
- 9002693
- Application Number:
- 13/342,128
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- B554331
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2012 Jan 02
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Asaad, Sameh, Kapur, Mohit, and Parker, Benjamin D. Wire like link for cycle reproducible and cycle accurate hardware accelerator. United States: N. p., 2015.
Web.
Asaad, Sameh, Kapur, Mohit, & Parker, Benjamin D. Wire like link for cycle reproducible and cycle accurate hardware accelerator. United States.
Asaad, Sameh, Kapur, Mohit, and Parker, Benjamin D. Tue .
"Wire like link for cycle reproducible and cycle accurate hardware accelerator". United States. https://www.osti.gov/servlets/purl/1177498.
@article{osti_1177498,
title = {Wire like link for cycle reproducible and cycle accurate hardware accelerator},
author = {Asaad, Sameh and Kapur, Mohit and Parker, Benjamin D},
abstractNote = {First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Apr 07 00:00:00 EDT 2015},
month = {Tue Apr 07 00:00:00 EDT 2015}
}
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Works referencing / citing this record:
Wire like link for cycle reproducible and cycle accurate hardware accelerator
patent, April 2015
- Asaad, Sameh W.; Kapur, Mohit; Parker, Benjamin D.
- US Patent Document 9,002,693