Scheduler for multiprocessor system switch with selective pairing

Gara, Alan; Gschwind, Michael Karl; Salapura, Valentina

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A - human necessities
A01 - agriculture
A21 - baking
A22 - butchering
A23 - foods or foodstuffs
A24 - tobacco
A41 - wearing apparel
A42 - headwear
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A44 - haberdashery
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A47 - furniture
A61 - medical or veterinary science
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A99 - subject matter not otherwise provided for in this section
B - performing operations
B01 - physical or chemical processes or apparatus in general
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B03 - separation of solid materials using liquids or using pneumatic tables or jigs
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D02 - yarns
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Title: Scheduler for multiprocessor system switch with selective pairing

Abstract

System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience.

Inventors:: Gara, Alan; Gschwind, Michael Karl; Salapura, Valentina

Issue Date:: Tue Jan 06 00:00:00 EST 2015

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1167015

Patent Number(s):: 8930752

Application Number:: 13/027,960

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Show more

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/1641 - {where the comparison is not performed by the redundant processing components}
G06F11/165 - {with continued operation after detection of the error}
G06F2201/845 - Systems in which the redundancy can be transformed in increased performance

Show less

DOE Contract Number:: B554331

Resource Type:: Patent

Resource Relation:: Patent File Date: 2011 Feb 15

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Gara, Alan, Gschwind, Michael Karl, and Salapura, Valentina. Scheduler for multiprocessor system switch with selective pairing.  United States: N. p., 2015. 
        Web.

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                    Gara, Alan, Gschwind, Michael Karl, & Salapura, Valentina. Scheduler for multiprocessor system switch with selective pairing.  United States.

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                    Gara, Alan, Gschwind, Michael Karl, and Salapura, Valentina. Tue .  
        "Scheduler for multiprocessor system switch with selective pairing".  United States.  https://www.osti.gov/servlets/purl/1167015.

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@article{osti_1167015,

  title        = {Scheduler for multiprocessor system switch with selective pairing},

  author       = {Gara, Alan and Gschwind, Michael Karl and Salapura, Valentina},

  abstractNote = {System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Tue Jan 06 00:00:00 EST 2015},

  month        = {Tue Jan 06 00:00:00 EST 2015}

}

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Similar Records

Title: Scheduler for multiprocessor system switch with selective pairing

Abstract

Citation Formats

Uncoupling a central processing unit from its associated hardware for interaction with data handling apparatus alien to the operating system controlling said unit and hardware patent, February 1995

Main memory system and checkpointing protocol for a fault-tolerant computer system using a read buffer patent, April 1998

Method of synchronizing a pair of central processor units for duplex, lock-step operation by copying data into a corresponding locations of another memory patent, May 1998

Storage access validation to data messages using partial storage address data indexed entries containing permissible address range validation for message source patent, October 1999

Method of non-intrusive testing for a process control interface system having triply redundant remote field units patent, October 1999

Fault tolerant computer system patent, October 2000

Error self-checking and recovery using lock-step processor pair architecture patent, May 2002

Multiprocessor with pair-wise high reliability mode, and method therefore patent, August 2004

Providing fault-tolerance by comparing addresses and data from redundant processors running in lock-step patent, March 2005

System recovery from errors for processor and associated components patent, September 2005

Emulation interface system patent, June 2006

Apparatus and methods for fault-tolerant computing using a switching fabric patent, June 2006

Method and apparatus for communicating information between lock stepped processors patent, December 2006

Architectural support for selective use of high-reliability mode in a computer system patent, October 2007

Core-level processor lockstepping patent, October 2007

Core redundancy in a chip multiprocessor for highly reliable systems patent, February 2008

Synchronous electronic control system and system control method patent, March 2008

Method and apparatus for seeding differences in lock-stepped processors patent, July 2008

Method and system of executing duplicate copies of a program in lock step patent, September 2008

Cross correlation tool for automated portfolio descriptive statistics patent, April 2009

System and method for a distributed crossbar network using a plurality of crossbars patent, July 2009

Cache coherency during resynchronization of self-correcting computer patent, November 2009

Method and device for switching over in a computer system having at least two execution units patent, February 2010

Selective availability in processor systems patent, May 2011

Auxiliary circuit structure in a split-lock dual processor system patent, November 2011

System recovery from errors for processor and associated components patent-application, October 2002

High reliability system, redundant construction control method, and program patent-application, September 2005

Delegated write for race avoidance in a processor patent-application, October 2005

Diagnostic memory dump method in a redundant processor patent-application, October 2005

System and method of executing program threads in a multi-threaded processor patent-application, October 2006

Method and apparatus for communicating information between lock stepped processors patent-application, March 2007

System with Configurable Functional Units and Method patent-application, February 2010

Resource Sharing to Reduce Implementation Costs in a Multicore Processor patent-application, July 2011

A Genetic Algorithm for Reliability-Oriented Task Assignment With<tex>$widetildek$</tex>Duplications in Distributed Systems journal, March 2006

The Stanford Hydra CMP journal, January 2000

Transactional Memory Coherence and Consistency journal, March 2004

Transactional memory: architectural support for lock-free data structures conference, January 1993

Uncoupling a central processing unit from its associated hardware for interaction with data handling apparatus alien to the operating system controlling said unit and hardware
patent, February 1995

Main memory system and checkpointing protocol for a fault-tolerant computer system using a read buffer
patent, April 1998

Method of synchronizing a pair of central processor units for duplex, lock-step operation by copying data into a corresponding locations of another memory
patent, May 1998

Storage access validation to data messages using partial storage address data indexed entries containing permissible address range validation for message source
patent, October 1999

Method of non-intrusive testing for a process control interface system having triply redundant remote field units
patent, October 1999

Fault tolerant computer system
patent, October 2000

Error self-checking and recovery using lock-step processor pair architecture
patent, May 2002

Multiprocessor with pair-wise high reliability mode, and method therefore
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Providing fault-tolerance by comparing addresses and data from redundant processors running in lock-step
patent, March 2005

System recovery from errors for processor and associated components
patent, September 2005

Emulation interface system
patent, June 2006

Apparatus and methods for fault-tolerant computing using a switching fabric
patent, June 2006

Method and apparatus for communicating information between lock stepped processors
patent, December 2006

Architectural support for selective use of high-reliability mode in a computer system
patent, October 2007

Core-level processor lockstepping
patent, October 2007

Core redundancy in a chip multiprocessor for highly reliable systems
patent, February 2008

Synchronous electronic control system and system control method
patent, March 2008

Method and apparatus for seeding differences in lock-stepped processors
patent, July 2008

Method and system of executing duplicate copies of a program in lock step
patent, September 2008

Cross correlation tool for automated portfolio descriptive statistics
patent, April 2009

System and method for a distributed crossbar network using a plurality of crossbars
patent, July 2009

Cache coherency during resynchronization of self-correcting computer
patent, November 2009

Method and device for switching over in a computer system having at least two execution units
patent, February 2010

Selective availability in processor systems
patent, May 2011

Auxiliary circuit structure in a split-lock dual processor system
patent, November 2011

System recovery from errors for processor and associated components
patent-application, October 2002

High reliability system, redundant construction control method, and program
patent-application, September 2005

Delegated write for race avoidance in a processor
patent-application, October 2005

Diagnostic memory dump method in a redundant processor
patent-application, October 2005

System and method of executing program threads in a multi-threaded processor
patent-application, October 2006

Method and apparatus for communicating information between lock stepped processors
patent-application, March 2007

System with Configurable Functional Units and Method
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Resource Sharing to Reduce Implementation Costs in a Multicore Processor
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A Genetic Algorithm for Reliability-Oriented Task Assignment With<tex>$widetildek$</tex>Duplications in Distributed Systems
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The Stanford Hydra CMP
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