Debugging a high performance computing program

Gooding, Thomas M.

Advanced Search OptionsAdvanced Search queries use a traditional Term Search. For more info, see our FAQ.

All Fields:

Patent Title:

Abstract:

Assignee:

Inventor(s):

Patent Number:

Patent Classification (CPC):

All Classifications
A - human necessities
A01 - agriculture
A21 - baking
A22 - butchering
A23 - foods or foodstuffs
A24 - tobacco
A41 - wearing apparel
A42 - headwear
A43 - footwear
A44 - haberdashery
A45 - hand or travelling articles
A46 - brushware
A47 - furniture
A61 - medical or veterinary science
A62 - life-saving
A63 - sports
A99 - subject matter not otherwise provided for in this section
B - performing operations
B01 - physical or chemical processes or apparatus in general
B02 - crushing, pulverising, or disintegrating
B03 - separation of solid materials using liquids or using pneumatic tables or jigs
B04 - centrifugal apparatus or machines for carrying-out physical or chemical processes
B05 - spraying or atomising in general
B06 - generating or transmitting mechanical vibrations in general
B07 - separating solids from solids
B08 - cleaning
B09 - disposal of solid waste
B21 - mechanical metal-working without essentially removing material
B22 - casting
B23 - machine tools
B24 - grinding
B25 - hand tools
B26 - hand cutting tools
B27 - working or preserving wood or similar material
B28 - working cement, clay, or stone
B29 - working of plastics
B30 - presses
B31 - making articles of paper, cardboard or material worked in a manner analogous to paper
B32 - layered products
B33 - additive manufacturing technology
B41 - printing
B42 - bookbinding
B43 - writing or drawing implements
B44 - decorative arts
B60 - vehicles in general
B61 - railways
B62 - land vehicles for travelling otherwise than on rails
B63 - ships or other waterborne vessels
B64 - aircraft
B65 - conveying
B66 - hoisting
B67 - opening, closing {or cleaning} bottles, jars or similar containers
B68 - saddlery
B81 - microstructural technology
B82 - nanotechnology
B99 - subject matter not otherwise provided for in this section
C - chemistry
C01 - inorganic chemistry
C02 - treatment of water, waste water, sewage, or sludge
C03 - glass
C04 - cements
C05 - fertilisers
C06 - explosives
C07 - organic chemistry
C08 - organic macromolecular compounds
C09 - dyes
C10 - petroleum, gas or coke industries
C11 - animal or vegetable oils, fats, fatty substances or waxes
C12 - biochemistry
C13 - sugar industry
C14 - skins
C21 - metallurgy of iron
C22 - metallurgy
C23 - coating metallic material
C25 - electrolytic or electrophoretic processes
C30 - crystal growth
C40 - combinatorial technology
C99 - subject matter not otherwise provided for in this section
D - textiles
D01 - natural or man-made threads or fibres
D02 - yarns
D03 - weaving
D04 - braiding
D05 - sewing
D06 - treatment of textiles or the like
D07 - ropes
D10 - indexing scheme associated with sublasses of section d, relating to textiles
D21 - paper-making
D99 - subject matter not otherwise provided for in this section
E - fixed constructions
E01 - construction of roads, railways, or bridges
E02 - hydraulic engineering
E03 - water supply
E04 - building
E05 - locks
E06 - doors, windows, shutters, or roller blinds in general
E21 - earth drilling
E99 - subject matter not otherwise provided for in this section
F - mechanical engineering
F01 - machines or engines in general
F02 - combustion engines
F03 - machines or engines for liquids
F04 - positive - displacement machines for liquids
F05 - indexing schemes relating to engines or pumps in various subclasses of classes f01-f04
F15 - fluid-pressure actuators
F16 - engineering elements and units
F17 - storing or distributing gases or liquids
F21 - lighting
F22 - steam generation
F23 - combustion apparatus
F24 - heating
F25 - refrigeration or cooling
F26 - drying
F27 - furnaces
F28 - heat exchange in general
F41 - weapons
F42 - ammunition
F99 - subject matter not otherwise provided for in this section
G - physics
G01 - measuring
G02 - optics
G03 - photography
G04 - horology
G05 - controlling
G06 - computing
G07 - checking-devices
G08 - signalling
G09 - education
G10 - musical instruments
G11 - information storage
G12 - instrument details
G16 - information and communication technology [ict] specially adapted for specific application fields
G21 - nuclear physics
G99 - subject matter not otherwise provided for in this section
H - electricity
H01 - basic electric elements
H02 - generation
H03 - basic electronic circuitry
H04 - electric communication technique
H05 - electric techniques not otherwise provided for
H99 - subject matter not otherwise provided for in this section
Y - new / cross sectional technologies
Y02 - technologies or applications for mitigation or adaptation against climate change
Y04 - information or communication technologies having an impact on other technology areas
Y10 - technical subjects covered by former uspc

More Options ...

Title: Debugging a high performance computing program

Abstract

Methods, apparatus, and computer program products are disclosed for debugging a high performance computing program by gathering lists of addresses of calling instructions for a plurality of threads of execution of the program, assigning the threads to groups in dependence upon the addresses, and displaying the groups to identify defective threads.

Inventors:: Gooding, Thomas M.

Issue Date:: Tue Aug 19 00:00:00 EDT 2014

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1150217

Patent Number(s):: 8813037

Application Number:: 13/780,215

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Show more

G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/3636 - {by tracing the execution of the program}
G06F11/3664 - {Environments for testing or debugging software}

Show less

DOE Contract Number:: B519700

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Gooding, Thomas M. Debugging a high performance computing program.  United States: N. p., 2014. 
        Web.

Copy to clipboard


                    Gooding, Thomas M. Debugging a high performance computing program.  United States.

Copy to clipboard


                    Gooding, Thomas M. Tue .  
        "Debugging a high performance computing program".  United States.  https://www.osti.gov/servlets/purl/1150217.

Copy to clipboard


                    
@article{osti_1150217,

  title        = {Debugging a high performance computing program},

  author       = {Gooding, Thomas M.},

  abstractNote = {Methods, apparatus, and computer program products are disclosed for debugging a high performance computing program by gathering lists of addresses of calling instructions for a plurality of threads of execution of the program, assigning the threads to groups in dependence upon the addresses, and displaying the groups to identify defective threads.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Tue Aug 19 00:00:00 EDT 2014},

  month        = {Tue Aug 19 00:00:00 EDT 2014}

}

Copy to clipboard

Patent:

Save / Share:

Export Metadata

Save to My Library

Works referenced in this record:

Processing system with dual buses
patent, January 1981

Richter, David
US Patent Document 4,245,344
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/4245344

Fault detection and redundancy management system
patent, January 1987

Julich, Paul M.; Pearce, Jeffrey B.
US Patent Document 4,634,110
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/4634110

Binary tree parallel processor
patent, August 1989

Stolfo, Salvatore J.; Miranker, Daniel Paul
US Patent Document 4,860,201
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/4860201

Parallel computer system
patent, July 1994

Douglas, David C.; Ganmukhi, Mahesh N.; Hill, Jeffrey V.
US Patent Document 5,333,268
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5333268

Torus networking method and apparatus having a switch for performing an I/O operation with an external device and changing torus size
patent, March 1998

Hayashi, Kenichi
US Patent Document 5,729,756
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5729756

Computer method for updating a network design
patent, October 1998

Tonelli, Daniel L.; Maloney, Kevin M.; Cronin, Kevin W.
US Patent Document 5,821,937
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5821937

Apparatus region-based detection of interference among reordered memory operations in a processor
patent, June 1999

Moreno, Jaime; Moudgill, Mavan
US Patent Document 5,918,005
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5918005

Distributed method and system for excluding components from a restoral route in a communications network
patent, August 1999

Croslin, William D.; Sellers, Steve; Sees, Mark W.
US Patent Document 5,941,992
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5941992

Integrated management of multiple networks with different topologies
patent, September 1999

Wong, Norman; Bellinger, Doug; Freen, Russ
US Patent Document 5,953,347
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5953347

Method and apparatus for run-time memory access checking and memory leak detection of a multi-threaded program
patent, September 1999

Rishi, Alok; Masamitsu, Jon A.
US Patent Document 5,953,530
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5953530

System for method for performing a context switch operation in a massively parallel computer system
patent, April 2000

Spiller, Cynthia J.
US Patent Document 6,047,122
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6047122

Apparatus and methods for connecting modules using remote switching
patent, March 2001

Carvey, Philip P.; Dally, William J.; Dennison, Larry R.
US Patent Document 6,205,532
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6205532

Tree network including arrangement for establishing sub-tree having a logical root below the network's physical root
patent, September 2002

Ganmukhi, Mahesh N.; Hill, Jeffrey V.; Wong-Chan, Monica C.
US Patent Document 6,449,667
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6449667

Method of identifying low quality links in a telecommunications network
patent, November 2004

Shah, Jasvantrai C.
US Patent Document 6,813,240
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6813240

Mesh protection service in a communications network
patent, January 2005

Desai, Premal; Lu, Biao; Tedijanto, Theodore Ernest
US Patent Document 6,848,062
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6848062

Peer-to-peer fault detection
patent, April 2005

Mora, Oscar; Pinate, Roger; Ponticelli, Roberto
US Patent Document 6,880,100
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6880100

Selective protection for ring topologies
patent, May 2005

Bruckman, Leon
US Patent Document 6,892,329
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6892329

Communication network and protocol which can efficiently maintain transmission across a disrupted network
patent, June 2005

Mahalingaiah, Rupaka
US Patent Document 6,912,196
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6912196

Routing scheme using preferred paths in a multi-path interconnection fabric in a storage network
patent, February 2006

Lee, Whay Sing; Rettberg, Randall D.
US Patent Document 7,007,189
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7007189

Discovery of nodes in an interconnection fabric
patent, April 2006

Lee, Whay Sing; Mortensen, Thomas M.
US Patent Document 7,027,413
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7027413

Application manager for monitoring and recovery of software based application processes
patent, April 2006

Maso, Brian; Noy, Oded
US Patent Document 7,028,225
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7028225

Message routing in a torus interconnect
patent, July 2006

Lee, Whay Sing; Talagala, Nisha; Chong, Jr., Fay
US Patent Document 7,080,156
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7080156

Deterministic error recovery protocol
patent, December 2006

Blumrich, Matthew A.; Chen, Dong; Gara, Alan
US Patent Document 7,149,920
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7149920

Identifying faulty network components during a network exploration
patent, April 2007

Bender, Carl A.; Rash, Nicholas P.
US Patent Document 7,200,118
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7200118

Fault isolation through no-overhead link level CRC
patent, April 2007

Chen, Dong; Coteus, Paul W.; Gara, Alan
US Patent Document 7,210,088
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7210088

Inter-working mesh telecommunications networks
patent, October 2007

Chow, Timothy; Lin, Philip J.; Mills, James D.
US Patent Document 7,289,428
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7289428

Directing a path verification request along a specific path to a mesh network switch to test operability of the specific path
patent, June 2008

Wakumoto, Shaun; Bare, Ballard C.; Ersoy, Cetin
US Patent Document 7,382,734
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7382734

Connection set-up extension for restoration path establishment in mesh networks
patent, November 2008

Doshi, Bharat Tarachand; Dziong, Zbigniew M.; Nagarajan, Ramesh
US Patent Document 7,451,340
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7451340

Transferring data in a parallel processing environment
patent, December 2008

Wentzlaff, David
US Patent Document 7,461,236
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7461236

Network designing device and computer-readable medium
patent, March 2009

Nakashima, Hisao; Hoshida, Takeshi; Akiyama, Yuichi
US Patent Document 7,505,414
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7505414

Multi-directional fault detection system
patent, March 2009

Archer, Charles J.; Pinnow, Kurt Walter; Ratterman, Joseph D.
US Patent Document 7,506,197
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7506197

Cell boundary fault detection system
patent, May 2009

Archer, Charles J.; Pinnow, Kurt Walter; Ratterman, Joseph D.
US Patent Document 7,529,963
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7529963

Bisectional fault detection system
patent, August 2009

Archer, Charles J.; Pinnow, Kurt Walter; Ratterman, Joseph D.
US Patent Document 7,571,345
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7571345

Executing scatter operation to parallel computer nodes by repeatedly broadcasting content of send buffer partition corresponding to each node upon bitwise OR operation
patent, October 2009

Archer, Charles J.; Ratterman, Joseph D.
US Patent Document 7,600,095
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7600095

Locating hardware faults in a data communications network of a parallel computer
patent, January 2010

Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.
US Patent Document 7,646,721
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7646721

Row fault detection system
patent, February 2010

Archer, Charles J.; Pinnow, Kurt Walter; Ratterman, Joseph D.
US Patent Document 7,669,075
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7669075

Global tree network for computing structures
patent-application, April 2004

Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.
US Patent Document 10/469000; 20040078493
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20040078493

Method and system of interconnecting processors of a parallel computer to facilitate torus partitioning
patent-application, June 2005

Stockmeyer, Larry J.
US Patent Application 10/734340; 20050132163
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20050132163

Optimizing layout of an application on a massively parallel supercomputer
patent-application, May 2006

Bhanot, Gyan V.; Gara, Alan; Heidelberger, Philip
US Patent Application 10/963101; 20060101104
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20060101104

Method, system and program product for communicating among processes in a symmetric multi-processing cluster environment
patent-application, July 2007

Jia, Bin; Treumann, Richard R.
US Patent Application 11/282011; 20070174558
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20070174558

Computer Hardware Fault Diagnosis
patent-application, October 2007

Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.
US Patent Application 1/279573; 20070242611
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20070242611

Executing an Allgather Operation on a Parallel Computer
patent-application, October 2007

Archer, Charles J.; Moreira, JOse F.; Ratterman, Joseph D.
US Patent Application 11/279620; 20070245122
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20070245122

Executing a Scatter Operation on a Parallel Computer
patent-application, October 2008

Archer, Charles J.; Ratterman, Joseph D.
US Patent Application 11/737286; 20080263320
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080263320

Parallel-Prefix Broadcast for a Parallel-Prefix Operation on a Parallel Computer
patent-application, October 2008

Archer, Charles J.; Peters, Amanda; Ricard, Gary R.
US Patent Application 11/737209; 20080263329
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080263329

Fault recovery on a parallel computer system with a torus network
patent-application, October 2008

Darrington, David L.; McCarthy, Patrick Joseph; Peters, Amanda
US Patent Application 11/736923; 20080263387
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20080263387

Link Failure Detection in a Parallel Computer
patent-application, February 2009

Archer, Charles J.; Blocksome, Michael A.; Megerian, Mark G.
US Patent Application 11/832940; 20090037773
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20090037773

Performing Collective Operations in a Distributed Processing System
patent-application, March 2013

Archer, Charles J.; Carey, James E.; Markland, Matthew W.
US Patent Application 13/679133; 20130081037
URL: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20130081037

An Overview of the BlueGene/L Supercomputer
conference, January 2002

Adiga, N. R.; Almasi, G.; Almasi, G. S.
ACM/IEEE SC 2002 Conference (SC'02)
https://doi.org/10.1109/SC.2002.10017

Similar Records in DOE Patents and OSTI.GOV collections:

Debugging a high performance computing program

Patent Gooding, Thomas M.

Methods, apparatus, and computer program products are disclosed for debugging a high performance computing program by gathering lists of addresses of calling instructions for a plurality of threads of execution of the program, assigning the threads to groups in dependence upon the addresses, and displaying the groups to identify defective threads.
Full Text Available
Failure detection in high-performance clusters and computers using chaotic map computations

Patent Rao, Nageswara S.

A programmable media includes a processing unit capable of independent operation in a machine that is capable of executing 10.sup.18 floating point operations per second. The processing unit is in communication with a memory element and an interconnect that couples computing nodes. The programmable media includes a logical unit configured to execute arithmetic functions, comparative functions, and/or logical functions. The processing unit is configured to detect computing component failures, memory element failures and/or interconnect failures by executing programming threads that generate one or more chaotic map trajectories. The central processing unit or graphical processing unit is configured to detect amore » « less
Full Text Available
Cloud object store for archive storage of high performance computing data using decoupling middleware

Patent Bent, John M.; Faibish, Sorin; Grider, Gary

Cloud object storage is enabled for archived data, such as checkpoints and results, of high performance computing applications using a middleware process. A plurality of archived files, such as checkpoint files and results, generated by a plurality of processes in a parallel computing system are stored by obtaining the plurality of archived files from the parallel computing system; converting the plurality of archived files to objects using a log structured file system middleware process; and providing the objects for storage in a cloud object storage system. The plurality of processes may run, for example, on a plurality of compute nodes.more » « less
Full Text Available
Cloud object store for checkpoints of high performance computing applications using decoupling middleware

Patent Bent, John M.; Faibish, Sorin; Grider, Gary

Cloud object storage is enabled for checkpoints of high performance computing applications using a middleware process. A plurality of files, such as checkpoint files, generated by a plurality of processes in a parallel computing system are stored by obtaining said plurality of files from said parallel computing system; converting said plurality of files to objects using a log structured file system middleware process; and providing said objects for storage in a cloud object storage system. The plurality of processes may run, for example, on a plurality of compute nodes. The log structured file system middleware process may be embodied, formore » « less
Full Text Available
Complex matrix multiplication operations with data pre-conditioning in a high performance computing architecture

Patent Eichenberger, Alexandre E; Gschwind, Michael K; Gunnels, John A

Mechanisms for performing a complex matrix multiplication operation are provided. A vector load operation is performed to load a first vector operand of the complex matrix multiplication operation to a first target vector register. The first vector operand comprises a real and imaginary part of a first complex vector value. A complex load and splat operation is performed to load a second complex vector value of a second vector operand and replicate the second complex vector value within a second target vector register. The second complex vector value has a real and imaginary part. A cross multiply add operation ismore » « less
Full Text Available

Similar Records

Title: Debugging a high performance computing program

Abstract

Citation Formats

Processing system with dual buses patent, January 1981

Fault detection and redundancy management system patent, January 1987

Binary tree parallel processor patent, August 1989

Parallel computer system patent, July 1994

Torus networking method and apparatus having a switch for performing an I/O operation with an external device and changing torus size patent, March 1998

Computer method for updating a network design patent, October 1998

Apparatus region-based detection of interference among reordered memory operations in a processor patent, June 1999

Distributed method and system for excluding components from a restoral route in a communications network patent, August 1999

Integrated management of multiple networks with different topologies patent, September 1999

Method and apparatus for run-time memory access checking and memory leak detection of a multi-threaded program patent, September 1999

System for method for performing a context switch operation in a massively parallel computer system patent, April 2000

Apparatus and methods for connecting modules using remote switching patent, March 2001

Tree network including arrangement for establishing sub-tree having a logical root below the network's physical root patent, September 2002

Method of identifying low quality links in a telecommunications network patent, November 2004

Mesh protection service in a communications network patent, January 2005

Peer-to-peer fault detection patent, April 2005

Selective protection for ring topologies patent, May 2005

Communication network and protocol which can efficiently maintain transmission across a disrupted network patent, June 2005

Routing scheme using preferred paths in a multi-path interconnection fabric in a storage network patent, February 2006

Discovery of nodes in an interconnection fabric patent, April 2006

Application manager for monitoring and recovery of software based application processes patent, April 2006

Message routing in a torus interconnect patent, July 2006

Deterministic error recovery protocol patent, December 2006

Identifying faulty network components during a network exploration patent, April 2007

Fault isolation through no-overhead link level CRC patent, April 2007

Inter-working mesh telecommunications networks patent, October 2007

Directing a path verification request along a specific path to a mesh network switch to test operability of the specific path patent, June 2008

Connection set-up extension for restoration path establishment in mesh networks patent, November 2008

Transferring data in a parallel processing environment patent, December 2008

Network designing device and computer-readable medium patent, March 2009

Multi-directional fault detection system patent, March 2009

Cell boundary fault detection system patent, May 2009

Bisectional fault detection system patent, August 2009

Executing scatter operation to parallel computer nodes by repeatedly broadcasting content of send buffer partition corresponding to each node upon bitwise OR operation patent, October 2009

Locating hardware faults in a data communications network of a parallel computer patent, January 2010

Row fault detection system patent, February 2010

Global tree network for computing structures patent-application, April 2004

Method and system of interconnecting processors of a parallel computer to facilitate torus partitioning patent-application, June 2005

Optimizing layout of an application on a massively parallel supercomputer patent-application, May 2006

Method, system and program product for communicating among processes in a symmetric multi-processing cluster environment patent-application, July 2007

Computer Hardware Fault Diagnosis patent-application, October 2007

Executing an Allgather Operation on a Parallel Computer patent-application, October 2007

Executing a Scatter Operation on a Parallel Computer patent-application, October 2008

Parallel-Prefix Broadcast for a Parallel-Prefix Operation on a Parallel Computer patent-application, October 2008

Fault recovery on a parallel computer system with a torus network patent-application, October 2008

Link Failure Detection in a Parallel Computer patent-application, February 2009

Performing Collective Operations in a Distributed Processing System patent-application, March 2013

An Overview of the BlueGene/L Supercomputer conference, January 2002

Processing system with dual buses
patent, January 1981

Fault detection and redundancy management system
patent, January 1987

Binary tree parallel processor
patent, August 1989

Parallel computer system
patent, July 1994

Torus networking method and apparatus having a switch for performing an I/O operation with an external device and changing torus size
patent, March 1998

Computer method for updating a network design
patent, October 1998

Apparatus region-based detection of interference among reordered memory operations in a processor
patent, June 1999

Distributed method and system for excluding components from a restoral route in a communications network
patent, August 1999

Integrated management of multiple networks with different topologies
patent, September 1999

Method and apparatus for run-time memory access checking and memory leak detection of a multi-threaded program
patent, September 1999

System for method for performing a context switch operation in a massively parallel computer system
patent, April 2000

Apparatus and methods for connecting modules using remote switching
patent, March 2001

Tree network including arrangement for establishing sub-tree having a logical root below the network's physical root
patent, September 2002

Method of identifying low quality links in a telecommunications network
patent, November 2004

Mesh protection service in a communications network
patent, January 2005

Peer-to-peer fault detection
patent, April 2005

Selective protection for ring topologies
patent, May 2005

Communication network and protocol which can efficiently maintain transmission across a disrupted network
patent, June 2005

Routing scheme using preferred paths in a multi-path interconnection fabric in a storage network
patent, February 2006

Discovery of nodes in an interconnection fabric
patent, April 2006

Application manager for monitoring and recovery of software based application processes
patent, April 2006

Message routing in a torus interconnect
patent, July 2006

Deterministic error recovery protocol
patent, December 2006

Identifying faulty network components during a network exploration
patent, April 2007

Fault isolation through no-overhead link level CRC
patent, April 2007

Inter-working mesh telecommunications networks
patent, October 2007

Directing a path verification request along a specific path to a mesh network switch to test operability of the specific path
patent, June 2008

Connection set-up extension for restoration path establishment in mesh networks
patent, November 2008

Transferring data in a parallel processing environment
patent, December 2008

Network designing device and computer-readable medium
patent, March 2009

Multi-directional fault detection system
patent, March 2009

Cell boundary fault detection system
patent, May 2009

Bisectional fault detection system
patent, August 2009

Executing scatter operation to parallel computer nodes by repeatedly broadcasting content of send buffer partition corresponding to each node upon bitwise OR operation
patent, October 2009

Locating hardware faults in a data communications network of a parallel computer
patent, January 2010

Row fault detection system
patent, February 2010

Global tree network for computing structures
patent-application, April 2004

Method and system of interconnecting processors of a parallel computer to facilitate torus partitioning
patent-application, June 2005

Optimizing layout of an application on a massively parallel supercomputer
patent-application, May 2006

Method, system and program product for communicating among processes in a symmetric multi-processing cluster environment
patent-application, July 2007

Computer Hardware Fault Diagnosis
patent-application, October 2007

Executing an Allgather Operation on a Parallel Computer
patent-application, October 2007

Executing a Scatter Operation on a Parallel Computer
patent-application, October 2008

Parallel-Prefix Broadcast for a Parallel-Prefix Operation on a Parallel Computer
patent-application, October 2008

Fault recovery on a parallel computer system with a torus network
patent-application, October 2008

Link Failure Detection in a Parallel Computer
patent-application, February 2009

Performing Collective Operations in a Distributed Processing System
patent-application, March 2013

An Overview of the BlueGene/L Supercomputer
conference, January 2002