Collective network for computer structures

Blumrich, Matthias A; Coteus, Paul W; Chen, Dong; Gara, Alan; Giampapa, Mark E; Heidelberger, Philip; Hoenicke, Dirk; Takken, Todd E; Steinmacher-Burow, Burkhard D; Vranas, Pavlos M

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Title: Collective network for computer structures

Abstract

A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to the needs of a processing algorithm.

Inventors:: Blumrich, Matthias A; Coteus, Paul W; Chen, Dong; Gara, Alan; Giampapa, Mark E; Heidelberger, Philip; Hoenicke, Dirk; Takken, Todd E; Steinmacher-Burow, Burkhard D; Vranas, Pavlos M

Issue Date:: Tue Jan 07 00:00:00 EST 2014

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1113767

Patent Number(s):: 8626957

Application Number:: 13/101,566

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/08 - Error detection or correction by redundancy in data representation, e.g. by using checking codes
G06F11/1423 - {by reconfiguration of paths}
G06F9/46 - Multiprogramming arrangements

H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03M - CODING
H03M13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
H04L1/0061 - {Error detection codes}
H04L1/08 - by repeating transmission, e.g. Verdan system {
H04L1/1607 - {Details of the supervisory signal}
H04L1/1867 - {Arrangements specific to the transmitter end}
H04L2001/0093 - {Point-to-multipoint}
H04L2001/0097 - {Relays}

Show less

DOE Contract Number:: B517552

Resource Type:: Patent

Resource Relation:: Patent File Date: 2011 May 05

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Blumrich, Matthias A, Coteus, Paul W, Chen, Dong, Gara, Alan, Giampapa, Mark E, Heidelberger, Philip, Hoenicke, Dirk, Takken, Todd E, Steinmacher-Burow, Burkhard D, and Vranas, Pavlos M. Collective network for computer structures.  United States: N. p., 2014. 
        Web.

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                    Blumrich, Matthias A, Coteus, Paul W, Chen, Dong, Gara, Alan, Giampapa, Mark E, Heidelberger, Philip, Hoenicke, Dirk, Takken, Todd E, Steinmacher-Burow, Burkhard D, & Vranas, Pavlos M. Collective network for computer structures.  United States.

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                    Blumrich, Matthias A, Coteus, Paul W, Chen, Dong, Gara, Alan, Giampapa, Mark E, Heidelberger, Philip, Hoenicke, Dirk, Takken, Todd E, Steinmacher-Burow, Burkhard D, and Vranas, Pavlos M. Tue .  
        "Collective network for computer structures".  United States.  https://www.osti.gov/servlets/purl/1113767.

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@article{osti_1113767,

  title        = {Collective network for computer structures},

  author       = {Blumrich, Matthias A and Coteus, Paul W and Chen, Dong and Gara, Alan and Giampapa, Mark E and Heidelberger, Philip and Hoenicke, Dirk and Takken, Todd E and Steinmacher-Burow, Burkhard D and Vranas, Pavlos M},

  abstractNote = {A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to the needs of a processing algorithm.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Tue Jan 07 00:00:00 EST 2014},

  month        = {Tue Jan 07 00:00:00 EST 2014}

}

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Global interrupt and barrier networks
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Arithmetic functions in torus and tree networks
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Similar Records

Title: Collective network for computer structures

Abstract

Citation Formats

Negotiation protocol for establishment of full duplex communication on a token ring network patent, May 1995

Reducing the complexities of the transmission control protocol for a high-speed networking environment patent, August 1995

Barrier and eureka synchronization architecture for multiprocessors patent, February 1998

Self-synchronous packet scrambler patent, November 1998

Multi-protocol dual fiber link laser diode controller and method patent, September 1999

Distributed precomputation of network signal paths with table-based link capacity control patent, February 2000

Apparatus and method for improved vector processing to support extended-length integer arithmetic patent, September 2001

Architecture for lightweight signaling in ATM networks patent, April 2003

Global interrupt and barrier networks patent, October 2008

Configuring compute nodes of a parallel computer in an operational group into a plurality of independent non-overlapping collective networks patent, March 2010

Interfacing apparatus and method for adapting Ethernet directly to physical channel patent-application, November 2001

Method and computer program product for internet protocol (IP)-flow classification in a wireless point to multi-point (PTMP) patent-application, April 2003

Global interrupt and barrier networks patent-application, April 2004

Arithmetic functions in torus and tree networks patent-application, April 2004

Global tree network for computing structures patent-application, April 2004

Class network routing patent-application, April 2004

Novel massively parallel supercomputer patent-application, May 2004

Deterministic error recovery protocol patent-application, April 2005

Negotiation protocol for establishment of full duplex communication on a token ring network
patent, May 1995

Reducing the complexities of the transmission control protocol for a high-speed networking environment
patent, August 1995

Barrier and eureka synchronization architecture for multiprocessors
patent, February 1998

Self-synchronous packet scrambler
patent, November 1998

Multi-protocol dual fiber link laser diode controller and method
patent, September 1999

Distributed precomputation of network signal paths with table-based link capacity control
patent, February 2000

Apparatus and method for improved vector processing to support extended-length integer arithmetic
patent, September 2001

Architecture for lightweight signaling in ATM networks
patent, April 2003

Global interrupt and barrier networks
patent, October 2008

Configuring compute nodes of a parallel computer in an operational group into a plurality of independent non-overlapping collective networks
patent, March 2010

Interfacing apparatus and method for adapting Ethernet directly to physical channel
patent-application, November 2001

Method and computer program product for internet protocol (IP)-flow classification in a wireless point to multi-point (PTMP)
patent-application, April 2003

Global interrupt and barrier networks
patent-application, April 2004

Arithmetic functions in torus and tree networks
patent-application, April 2004

Global tree network for computing structures
patent-application, April 2004

Class network routing
patent-application, April 2004

Novel massively parallel supercomputer
patent-application, May 2004

Deterministic error recovery protocol
patent-application, April 2005