Distributed trace using central performance counter memory

Satterfield, David L.; Sexton, James C.

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Title: Distributed trace using central performance counter memory

Abstract

A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit.

Inventors:: Satterfield, David L.; Sexton, James C.

Issue Date:: Tue Oct 22 00:00:00 EDT 2013

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1107594

Patent Number(s):: 8566484

Application Number:: 13/590,879

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F11/3476 - {Data logging
G06F11/348 - {Circuit details, i.e. tracer hardware}
G06F11/3495 - {for systems}
G06F2201/88 - Monitoring involving counting

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02D - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
Y02D10/00 - Energy efficient computing

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DOE Contract Number:: B554331

Resource Type:: Patent

Resource Relation:: Patent File Date: 0012 Aug 21

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Satterfield, David L., and Sexton, James C. Distributed trace using central performance counter memory.  United States: N. p., 2013. 
        Web.

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                    Satterfield, David L., & Sexton, James C. Distributed trace using central performance counter memory.  United States.

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                    Satterfield, David L., and Sexton, James C. Tue .  
        "Distributed trace using central performance counter memory".  United States.  https://www.osti.gov/servlets/purl/1107594.

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@article{osti_1107594,

  title        = {Distributed trace using central performance counter memory},

  author       = {Satterfield, David L. and Sexton, James C.},

  abstractNote = {A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Tue Oct 22 00:00:00 EDT 2013},

  month        = {Tue Oct 22 00:00:00 EDT 2013}

}

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Works referenced in this record:

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Method and apparatus for obtaining trace information of multiple processors on an SoC using a segmented trace ring bus to enable a flexible trace output configuration
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Agrawal, Sumeet; Glew, Andrew F.; Franklin, Patrick
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Similar Records

Title: Distributed trace using central performance counter memory

Abstract

Citation Formats

Method, apparatus and computer program product for efficient per thread performance information patent, August 2005

Opportunistic improvement of MMIO request handling based on target reporting of space requirements patent, November 2011

Performance monitor synchronization in a multiprocessor system patent, November 2002

Method and apparatus for obtaining trace information of multiple processors on an SoC using a segmented trace ring bus to enable a flexible trace output configuration patent, June 2010

Apparatus for monitoring data transfers of an oemi channel interface patent, March 1994

Integrated circuit patent, March 2007

3D virtual environment creation management and delivery system patent, May 2000

Centralized performance monitoring architecture patent, March 1999

Memory in a programmable logic device patent, September 1998

Simultaneous real-time trace and debug for multiple processing core systems on a chip patent, July 2006

Method, apparatus and computer program product for efficient per thread performance information
patent, August 2005

Opportunistic improvement of MMIO request handling based on target reporting of space requirements
patent, November 2011

Performance monitor synchronization in a multiprocessor system
patent, November 2002

Method and apparatus for obtaining trace information of multiple processors on an SoC using a segmented trace ring bus to enable a flexible trace output configuration
patent, June 2010

Apparatus for monitoring data transfers of an oemi channel interface
patent, March 1994

Integrated circuit
patent, March 2007

3D virtual environment creation management and delivery system
patent, May 2000

Centralized performance monitoring architecture
patent, March 1999

Memory in a programmable logic device
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Simultaneous real-time trace and debug for multiple processing core systems on a chip
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