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Title: Class network routing

Abstract

Class network routing is implemented in a network such as a computer network comprising a plurality of parallel compute processors at nodes thereof. Class network routing allows a compute processor to broadcast a message to a range (one or more) of other compute processors in the computer network, such as processors in a column or a row. Normally this type of operation requires a separate message to be sent to each processor. With class network routing pursuant to the invention, a single message is sufficient, which generally reduces the total number of messages in the network as well as the latency to do a broadcast. Class network routing is also applied to dense matrix inversion algorithms on distributed memory parallel supercomputers with hardware class function (multicast) capability. This is achieved by exploiting the fact that the communication patterns of dense matrix inversion can be served by hardware class functions, which results in faster execution times.

Inventors:
 [1];  [2];  [3];  [4];  [5];  [6];  [7];  [5];  [5];  [8]
  1. Princeton, NJ
  2. Ridgefield, CT
  3. Croton On Hudson, NY
  4. Yorktown Heights, NY
  5. Mount Kisco, NY
  6. Irvington, NY
  7. Cortlandt Manor, NY
  8. Bedford Hills, NY
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
988822
Patent Number(s):
7587516
Application Number:
10/468,999
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
H - ELECTRICITY H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR H05K - PRINTED CIRCUITS
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
W-7405-ENG-48
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Bhanot, Gyan, Blumrich, Matthias A, Chen, Dong, Coteus, Paul W, Gara, Alan G, Giampapa, Mark E, Heidelberger, Philip, Steinmacher-Burow, Burkhard D, Takken, Todd E, and Vranas, Pavlos M. Class network routing. United States: N. p., 2009. Web.
Bhanot, Gyan, Blumrich, Matthias A, Chen, Dong, Coteus, Paul W, Gara, Alan G, Giampapa, Mark E, Heidelberger, Philip, Steinmacher-Burow, Burkhard D, Takken, Todd E, & Vranas, Pavlos M. Class network routing. United States.
Bhanot, Gyan, Blumrich, Matthias A, Chen, Dong, Coteus, Paul W, Gara, Alan G, Giampapa, Mark E, Heidelberger, Philip, Steinmacher-Burow, Burkhard D, Takken, Todd E, and Vranas, Pavlos M. Tue . "Class network routing". United States. https://www.osti.gov/servlets/purl/988822.
@article{osti_988822,
title = {Class network routing},
author = {Bhanot, Gyan and Blumrich, Matthias A and Chen, Dong and Coteus, Paul W and Gara, Alan G and Giampapa, Mark E and Heidelberger, Philip and Steinmacher-Burow, Burkhard D and Takken, Todd E and Vranas, Pavlos M},
abstractNote = {Class network routing is implemented in a network such as a computer network comprising a plurality of parallel compute processors at nodes thereof. Class network routing allows a compute processor to broadcast a message to a range (one or more) of other compute processors in the computer network, such as processors in a column or a row. Normally this type of operation requires a separate message to be sent to each processor. With class network routing pursuant to the invention, a single message is sufficient, which generally reduces the total number of messages in the network as well as the latency to do a broadcast. Class network routing is also applied to dense matrix inversion algorithms on distributed memory parallel supercomputers with hardware class function (multicast) capability. This is achieved by exploiting the fact that the communication patterns of dense matrix inversion can be served by hardware class functions, which results in faster execution times.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2009},
month = {9}
}

Works referenced in this record:

Multicast routing in internetworks and extended LANs
conference, January 1988


Performance Evaluation of Multicast Wormhole Routing in 2d-Torus Multicomputers
journal, September 1992


A systolic architecture for fast dense matrix inversion
journal, March 1989


An optimal scheduling procedure for matrix inversion on linear array at a processor level
journal, August 1994