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Title: On-Chip AC self-test controller

Abstract

A system for performing AC self-test on an integrated circuit that includes a system clock for normal operation is provided. The system includes the system clock, self-test circuitry, a first and second test register to capture and launch test data in response to a sequence of data pulses, and a logic circuit to be tested. The self-test circuitry includes an AC self-test controller and a clock splitter. The clock splitter generates the sequence of data pulses including a long data capture pulse followed by an at speed data launch pulse and an at speed data capture pulse followed by a long data launch pulse. The at speed data launch pulse and the at speed data capture pulse are generated for a common cycle of the system clock.

Inventors:
 [1];  [2];  [3]
  1. Rhinebeck, NY
  2. Poughkeepsie, NY
  3. Fishkill, NY
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
988588
Patent Number(s):
7,596,734
Application Number:
12/185,172
Assignee:
International Business Machines Corporation (Armonk, NY)
DOE Contract Number:  
W-7405-ENG-48
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
47 OTHER INSTRUMENTATION

Citation Formats

Flanagan, John D, Herring, Jay R, and Lo, Tin-Chee. On-Chip AC self-test controller. United States: N. p., 2009. Web.
Flanagan, John D, Herring, Jay R, & Lo, Tin-Chee. On-Chip AC self-test controller. United States.
Flanagan, John D, Herring, Jay R, and Lo, Tin-Chee. Tue . "On-Chip AC self-test controller". United States. https://www.osti.gov/servlets/purl/988588.
@article{osti_988588,
title = {On-Chip AC self-test controller},
author = {Flanagan, John D and Herring, Jay R and Lo, Tin-Chee},
abstractNote = {A system for performing AC self-test on an integrated circuit that includes a system clock for normal operation is provided. The system includes the system clock, self-test circuitry, a first and second test register to capture and launch test data in response to a sequence of data pulses, and a logic circuit to be tested. The self-test circuitry includes an AC self-test controller and a clock splitter. The clock splitter generates the sequence of data pulses including a long data capture pulse followed by an at speed data launch pulse and an at speed data capture pulse followed by a long data launch pulse. The at speed data launch pulse and the at speed data capture pulse are generated for a common cycle of the system clock.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2009},
month = {9}
}

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