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Title: Single-poly EEPROM cell with lightly doped MOS capacitors

Abstract

An Electrically Erasable Programmable Read Only Memory (EEPROM) memory cell and a method of operation are disclosed for creating an EEPROM memory cell in a standard CMOS process. A single polysilicon layer is used in combination with lightly doped MOS capacitors. The lightly doped capacitors employed in the EEPROM memory cell can be asymmetrical in design. Asymmetrical capacitors reduce area. Further capacitance variation caused by inversion can also be reduced by using multiple control capacitors. In addition, the use of multiple tunneling capacitors provides the benefit of customized tunneling paths.

Inventors:
 [1];  [2];  [3];  [4]
  1. New Hope, MN
  2. Maple Grove, MN
  3. Mound, MN
  4. Golden Valley, MN
Issue Date:
Research Org.:
National Energy Technology Laboratory (NETL), Pittsburgh, PA, Morgantown, WV (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
981823
Patent Number(s):
7378705
Application Number:
11/217,829
Assignee:
Honeywell International, Inc. (Morristown, NJ)
Patent Classifications (CPCs):
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
DOE Contract Number:  
FC26-03NT41834
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Riekels, James E, Lucking, Thomas B, Larsen, Bradley J, and Gardner, Gary R. Single-poly EEPROM cell with lightly doped MOS capacitors. United States: N. p., 2008. Web.
Riekels, James E, Lucking, Thomas B, Larsen, Bradley J, & Gardner, Gary R. Single-poly EEPROM cell with lightly doped MOS capacitors. United States.
Riekels, James E, Lucking, Thomas B, Larsen, Bradley J, and Gardner, Gary R. Tue . "Single-poly EEPROM cell with lightly doped MOS capacitors". United States. https://www.osti.gov/servlets/purl/981823.
@article{osti_981823,
title = {Single-poly EEPROM cell with lightly doped MOS capacitors},
author = {Riekels, James E and Lucking, Thomas B and Larsen, Bradley J and Gardner, Gary R},
abstractNote = {An Electrically Erasable Programmable Read Only Memory (EEPROM) memory cell and a method of operation are disclosed for creating an EEPROM memory cell in a standard CMOS process. A single polysilicon layer is used in combination with lightly doped MOS capacitors. The lightly doped capacitors employed in the EEPROM memory cell can be asymmetrical in design. Asymmetrical capacitors reduce area. Further capacitance variation caused by inversion can also be reduced by using multiple control capacitors. In addition, the use of multiple tunneling capacitors provides the benefit of customized tunneling paths.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2008},
month = {5}
}

Works referenced in this record:

Temperature dependence of Fowler-Nordheim injection from accumulated n-type silicon into silicon dioxide
journal, May 1993


Modeling of the intrinsic retention characteristics of FLOTOX EEPROM cells under elevated temperature conditions
journal, April 1995


A new extrapolation law for data-retention time-to-failure of nonvolatile memories
journal, May 1999


A single-poly EEPROM cell in SIMOX technology for high-temperature applications up to 250/spl deg/C
journal, November 1997


A 1-Kbit EEPROM in SIMOX technology for high-temperature applications up to 250/spl deg/C
journal, October 2000


Experimental and theoretical investigation of nonvolatile memory data-retention
journal, July 1999


A single poly EEPROM cell structure for use in standard CMOS processes
journal, March 1994


An experimental 5-V-only 256-kbit CMOS EEPROM with a high-performance single-polysilicon cell
journal, October 1986