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Title: Global interrupt and barrier networks

Abstract

A system and method for generating global asynchronous signals in a computing structure. Particularly, a global interrupt and barrier network is implemented that implements logic for generating global interrupt and barrier signals for controlling global asynchronous operations performed by processing elements at selected processing nodes of a computing structure in accordance with a processing algorithm; and includes the physical interconnecting of the processing nodes for communicating the global interrupt and barrier signals to the elements via low-latency paths. The global asynchronous signals respectively initiate interrupt and barrier operations at the processing nodes at times selected for optimizing performance of the processing algorithms. In one embodiment, the global interrupt and barrier network is implemented in a scalable, massively parallel supercomputing device structure comprising a plurality of processing nodes interconnected by multiple independent networks, with each node including one or more processing elements for performing computation or communication activity as required when performing parallel algorithm operations. One multiple independent network includes a global tree network for enabling high-speed global tree communications among global tree network nodes or sub-trees thereof. The global interrupt and barrier network may operate in parallel with the global tree network for providing global asynchronous sideband signals.

Inventors:
 [1];  [2];  [3];  [4];  [5];  [6];  [3];  [4];  [4]
  1. Ridgefield, CT
  2. Croton-On-Hudson, NY
  3. Yorktown Heights, NY
  4. Mount Kisco, NY
  5. Irvington, NY
  6. Cortlandt Manor, NY
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
957016
Patent Number(s):
7444385
Application Number:
10/468,997
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
H - ELECTRICITY H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR H05K - PRINTED CIRCUITS
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
DOE Contract Number:  
W-7405-ENG-48
Resource Type:
Patent
Country of Publication:
United States
Language:
English

Citation Formats

Blumrich, Matthias A, Chen, Dong, Coteus, Paul W, Gara, Alan G, Giampapa, Mark E, Heidelberger, Philip, Kopcsay, Gerard V, Steinmacher-Burow, Burkhard D, and Takken, Todd E. Global interrupt and barrier networks. United States: N. p., 2008. Web.
Blumrich, Matthias A, Chen, Dong, Coteus, Paul W, Gara, Alan G, Giampapa, Mark E, Heidelberger, Philip, Kopcsay, Gerard V, Steinmacher-Burow, Burkhard D, & Takken, Todd E. Global interrupt and barrier networks. United States.
Blumrich, Matthias A, Chen, Dong, Coteus, Paul W, Gara, Alan G, Giampapa, Mark E, Heidelberger, Philip, Kopcsay, Gerard V, Steinmacher-Burow, Burkhard D, and Takken, Todd E. Tue . "Global interrupt and barrier networks". United States. https://www.osti.gov/servlets/purl/957016.
@article{osti_957016,
title = {Global interrupt and barrier networks},
author = {Blumrich, Matthias A and Chen, Dong and Coteus, Paul W and Gara, Alan G and Giampapa, Mark E and Heidelberger, Philip and Kopcsay, Gerard V and Steinmacher-Burow, Burkhard D and Takken, Todd E},
abstractNote = {A system and method for generating global asynchronous signals in a computing structure. Particularly, a global interrupt and barrier network is implemented that implements logic for generating global interrupt and barrier signals for controlling global asynchronous operations performed by processing elements at selected processing nodes of a computing structure in accordance with a processing algorithm; and includes the physical interconnecting of the processing nodes for communicating the global interrupt and barrier signals to the elements via low-latency paths. The global asynchronous signals respectively initiate interrupt and barrier operations at the processing nodes at times selected for optimizing performance of the processing algorithms. In one embodiment, the global interrupt and barrier network is implemented in a scalable, massively parallel supercomputing device structure comprising a plurality of processing nodes interconnected by multiple independent networks, with each node including one or more processing elements for performing computation or communication activity as required when performing parallel algorithm operations. One multiple independent network includes a global tree network for enabling high-speed global tree communications among global tree network nodes or sub-trees thereof. The global interrupt and barrier network may operate in parallel with the global tree network for providing global asynchronous sideband signals.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2008},
month = {10}
}

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