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Title: Heterogeneously integrated microsystem-on-a-chip

Abstract

A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.

Inventors:
 [1]
  1. Albuquerque, NM
Issue Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
936111
Patent Number(s):
7335972
Application Number:
10/713,374
Assignee:
Sandia Corporation (Albuquerque, NM)
Patent Classifications (CPCs):
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
B - PERFORMING OPERATIONS B81 - MICROSTRUCTURAL TECHNOLOGY B81C - PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING

Citation Formats

Chanchani, Rajen. Heterogeneously integrated microsystem-on-a-chip. United States: N. p., 2008. Web.
Chanchani, Rajen. Heterogeneously integrated microsystem-on-a-chip. United States.
Chanchani, Rajen. Tue . "Heterogeneously integrated microsystem-on-a-chip". United States. https://www.osti.gov/servlets/purl/936111.
@article{osti_936111,
title = {Heterogeneously integrated microsystem-on-a-chip},
author = {Chanchani, Rajen},
abstractNote = {A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2008},
month = {2}
}

Patent:

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