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Title: Formation of low resistivity titanium silicide gates in semiconductor integrated circuits

Abstract

A method of forming a titanium silicide (69) includes the steps of forming a transistor having a source region (58), a drain region (60) and a gate structure (56) and forming a titanium layer (66) over the transistor. A first anneal is performed with a laser anneal at an energy level that causes the titanium layer (66) to react with the gate structure (56) to form a high resistivity titanium silicide phase (68) having substantially small grain sizes. The unreacted portions of the titanium layer (66) are removed and a second anneal is performed, thereby causing the high resistivity titanium silicide phase (68) to convert to a low resistivity titanium silicide phase (69). The small grain sizes obtained by the first anneal allow low resistivity titanium silicide phase (69) to be achieved at device geometries less than about 0.25 micron.

Inventors:
 [1]
  1. Sunnyvale, CA
Issue Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
935560
Patent Number(s):
5937325
Application Number:
08/966,306
Assignee:
Advanced Micro Devices, Inc. (Sunnyvale, CA)
Patent Classifications (CPCs):
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
DOE Contract Number:  
W-7405-ENG-48
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CHEMISTRY

Citation Formats

Ishida, Emi. Formation of low resistivity titanium silicide gates in semiconductor integrated circuits. United States: N. p., 1999. Web.
Ishida, Emi. Formation of low resistivity titanium silicide gates in semiconductor integrated circuits. United States.
Ishida, Emi. Tue . "Formation of low resistivity titanium silicide gates in semiconductor integrated circuits". United States. https://www.osti.gov/servlets/purl/935560.
@article{osti_935560,
title = {Formation of low resistivity titanium silicide gates in semiconductor integrated circuits},
author = {Ishida, Emi},
abstractNote = {A method of forming a titanium silicide (69) includes the steps of forming a transistor having a source region (58), a drain region (60) and a gate structure (56) and forming a titanium layer (66) over the transistor. A first anneal is performed with a laser anneal at an energy level that causes the titanium layer (66) to react with the gate structure (56) to form a high resistivity titanium silicide phase (68) having substantially small grain sizes. The unreacted portions of the titanium layer (66) are removed and a second anneal is performed, thereby causing the high resistivity titanium silicide phase (68) to convert to a low resistivity titanium silicide phase (69). The small grain sizes obtained by the first anneal allow low resistivity titanium silicide phase (69) to be achieved at device geometries less than about 0.25 micron.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1999},
month = {8}
}

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