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Title: Radiation-hardened transistor and integrated circuit

Abstract

A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

Inventors:
 [1]
  1. Albuquerque, NM
Issue Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
919904
Patent Number(s):
7298010
Application Number:
11/358,391
Assignee:
Sandia Corporation (Albuquerque, NM)
Patent Classifications (CPCs):
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Patent
Country of Publication:
United States
Language:
English

Citation Formats

Ma, Kwok K. Radiation-hardened transistor and integrated circuit. United States: N. p., 2007. Web.
Ma, Kwok K. Radiation-hardened transistor and integrated circuit. United States.
Ma, Kwok K. Tue . "Radiation-hardened transistor and integrated circuit". United States. https://www.osti.gov/servlets/purl/919904.
@article{osti_919904,
title = {Radiation-hardened transistor and integrated circuit},
author = {Ma, Kwok K},
abstractNote = {A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2007},
month = {11}
}

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Works referenced in this record:

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MeV implants boost device design
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  • Mavis, D. G.; Eaton, P. H.
  • 2002 IEEE International Reliability Physics Symposium Proceedings. 40th Annual, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320)
  • https://doi.org/10.1109/RELPHY.2002.996639

Upset hardened memory design for submicron CMOS technology
journal, January 1996