Interconnection arrangement of routers of processor boards in array of cabinets supporting secure physical partition
Abstract
A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure includes routers in service or compute processor boards distributed in an array of cabinets connected in series on each board and to respective routers in neighboring row cabinet boards with the routers in series connection coupled to routers in series connection in respective neighboring column cabinet boards. The array can include disconnect cabinets or respective routers in all boards in each cabinet connected in a toroid. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.
- Inventors:
-
- Albuquerque, NM
- Issue Date:
- Research Org.:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 913113
- Patent Number(s):
- 7246217
- Application Number:
- 11/110,344
- Assignee:
- Sandia Corporation (Albuquerque, NM)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC04-94AL8500
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Tomkins, James L, and Camp, William J. Interconnection arrangement of routers of processor boards in array of cabinets supporting secure physical partition. United States: N. p., 2007.
Web.
Tomkins, James L, & Camp, William J. Interconnection arrangement of routers of processor boards in array of cabinets supporting secure physical partition. United States.
Tomkins, James L, and Camp, William J. Tue .
"Interconnection arrangement of routers of processor boards in array of cabinets supporting secure physical partition". United States. https://www.osti.gov/servlets/purl/913113.
@article{osti_913113,
title = {Interconnection arrangement of routers of processor boards in array of cabinets supporting secure physical partition},
author = {Tomkins, James L and Camp, William J},
abstractNote = {A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure includes routers in service or compute processor boards distributed in an array of cabinets connected in series on each board and to respective routers in neighboring row cabinet boards with the routers in series connection coupled to routers in series connection in respective neighboring column cabinet boards. The array can include disconnect cabinets or respective routers in all boards in each cabinet connected in a toroid. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Jul 17 00:00:00 EDT 2007},
month = {Tue Jul 17 00:00:00 EDT 2007}
}
Works referenced in this record:
Massively parallel computing using commodity components
journal, February 2000
- Brightwell, Ron; Fisk, Lee Ann; Greenberg, David S.
- Parallel Computing, Vol. 26, Issue 2-3
Scalable parallel application launch on Cplant#8482;
conference, January 2001
- Brightwell, Ron; Fisk, Lee Ann
- Proceedings of the 2001 ACM/IEEE conference on Supercomputing (CDROM) - Supercomputing '01