Fast Low-Cost Multiple Sensor Readout System
Abstract
A low resolution data acquisition system is presented. The data acquisition system has a plurality of readout modules serially connected to a controller. Each readout module has a FPGA in communication with analog to digital (A/D) converters, which are connected to sensors. The A/D converter has eight bit or lower resolution. The FPGA detects when a command is addressed to it and commands the A/D converters to convert analog sensor data into digital data. The digital data is sent on a high speed serial communication bus to the controller. A graphical display is used in one embodiment to indicate if a sensor reading is outside of a predetermined range.
- Inventors:
-
- Ames, IA
- College Park, MD
- Marshalltown, IA
- Issue Date:
- Research Org.:
- Iowa State Univ., Ames, IA (United States)
- OSTI Identifier:
- 880014
- Patent Number(s):
- 6717541
- Application Number:
- 10/425495
- Assignee:
- Iowa State University Research Foundation, Inc. (Ames, IA)
- Patent Classifications (CPCs):
-
G - PHYSICS G01 - MEASURING G01D - MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- FG02-91ER40634
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Carter-Lewis, David, Krennich, Frank, Le Bohec, Stephane, Petry, Dirk, and Sleege, Gary. Fast Low-Cost Multiple Sensor Readout System. United States: N. p., 2004.
Web.
Carter-Lewis, David, Krennich, Frank, Le Bohec, Stephane, Petry, Dirk, & Sleege, Gary. Fast Low-Cost Multiple Sensor Readout System. United States.
Carter-Lewis, David, Krennich, Frank, Le Bohec, Stephane, Petry, Dirk, and Sleege, Gary. Tue .
"Fast Low-Cost Multiple Sensor Readout System". United States. https://www.osti.gov/servlets/purl/880014.
@article{osti_880014,
title = {Fast Low-Cost Multiple Sensor Readout System},
author = {Carter-Lewis, David and Krennich, Frank and Le Bohec, Stephane and Petry, Dirk and Sleege, Gary},
abstractNote = {A low resolution data acquisition system is presented. The data acquisition system has a plurality of readout modules serially connected to a controller. Each readout module has a FPGA in communication with analog to digital (A/D) converters, which are connected to sensors. The A/D converter has eight bit or lower resolution. The FPGA detects when a command is addressed to it and commands the A/D converters to convert analog sensor data into digital data. The digital data is sent on a high speed serial communication bus to the controller. A graphical display is used in one embodiment to indicate if a sensor reading is outside of a predetermined range.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2004},
month = {4}
}
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