Variable Delay Element For Jitter Control In High Speed Data Links
Abstract
A circuit and method for decreasing the amount of jitter present at the receiver input of high speed data links which uses a driver circuit for input from a high speed data link which comprises a logic circuit having a first section (1) which provides data latches, a second section (2) which provides a circuit generates a pre-destorted output and for compensating for level dependent jitter having an OR function element and a NOR function element each of which is coupled to two inputs and to a variable delay element as an input which provides a bi-modal delay for pulse width pre-distortion, a third section (3) which provides a muxing circuit, and a forth section (4) for clock distribution in the driver circuit. A fifth section is used for logic testing the driver circuit.
- Inventors:
-
- Shokan, NY
- Issue Date:
- OSTI Identifier:
- 879653
- Patent Number(s):
- 6404257
- Application Number:
- 09/584028
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Livolsi, Robert R. Variable Delay Element For Jitter Control In High Speed Data Links. United States: N. p., 2002.
Web.
Livolsi, Robert R. Variable Delay Element For Jitter Control In High Speed Data Links. United States.
Livolsi, Robert R. Tue .
"Variable Delay Element For Jitter Control In High Speed Data Links". United States. https://www.osti.gov/servlets/purl/879653.
@article{osti_879653,
title = {Variable Delay Element For Jitter Control In High Speed Data Links},
author = {Livolsi, Robert R},
abstractNote = {A circuit and method for decreasing the amount of jitter present at the receiver input of high speed data links which uses a driver circuit for input from a high speed data link which comprises a logic circuit having a first section (1) which provides data latches, a second section (2) which provides a circuit generates a pre-destorted output and for compensating for level dependent jitter having an OR function element and a NOR function element each of which is coupled to two inputs and to a variable delay element as an input which provides a bi-modal delay for pulse width pre-distortion, a third section (3) which provides a muxing circuit, and a forth section (4) for clock distribution in the driver circuit. A fifth section is used for logic testing the driver circuit.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2002},
month = {6}
}