Wide tracking range, auto ranging, low jitter phase lock loop for swept and fixed frequency systems
Abstract
The present invention provides a wide tracking range phase locked loop (PLL) circuit that achieves minimal jitter in a recovered clock signal, regardless of the source of the jitter (i.e. whether it is in the source or the transmission media). The present invention PLL has automatic harmonic lockout detection circuitry via a novel lock and seek control logic in electrical communication with a programmable frequency discriminator and a code balance detector. (The frequency discriminator enables preset of a frequency window of upper and lower frequency limits to derive a programmable range within which signal acquisition is effected. The discriminator works in combination with the code balance detector circuit to minimize the sensitivity of the PLL circuit to random data in the data stream). In addition, the combination of a differential loop integrator with the lock and seek control logic obviates a code preamble and guarantees signal acquisition without harmonic lockup. An adaptive cable equalizer is desirably used in combination with the present invention PLL to recover encoded transmissions containing a clock and/or data. The equalizer automatically adapts to equalize short haul cable lengths of coaxial and twisted pair cables or wires and provides superior jitter performance itself. The combination ofmore »
- Inventors:
-
- Manorville, NY
- Issue Date:
- Research Org.:
- Brookhaven National Laboratory (BNL), Upton, NY (United States)
- OSTI Identifier:
- 874076
- Patent Number(s):
- 6307411
- Assignee:
- Brookhaven Science Associates (Upton, NY)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03L - AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- DOE Contract Number:
- AC02-98CH10886
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- wide; tracking; range; auto; ranging; jitter; phase; lock; loop; swept; fixed; frequency; systems; provides; locked; pll; circuit; achieves; minimal; recovered; clock; signal; regardless; source; transmission; media; automatic; harmonic; lockout; detection; circuitry; via; novel; seek; control; logic; electrical; communication; programmable; discriminator; code; balance; detector; enables; preset; window; upper; limits; derive; acquisition; effected; combination; minimize; sensitivity; random; data; stream; addition; differential; integrator; obviates; preamble; guarantees; lockup; adaptive; cable; equalizer; desirably; recover; encoded; transmissions; containing; andor; automatically; adapts; equalize; haul; lengths; coaxial; twisted; pair; cables; wires; superior; performance; desirable; permits; significant; detector circuit; fixed frequency; clock signal; /327/375/
Citation Formats
Kerner, Thomas M. Wide tracking range, auto ranging, low jitter phase lock loop for swept and fixed frequency systems. United States: N. p., 2001.
Web.
Kerner, Thomas M. Wide tracking range, auto ranging, low jitter phase lock loop for swept and fixed frequency systems. United States.
Kerner, Thomas M. Mon .
"Wide tracking range, auto ranging, low jitter phase lock loop for swept and fixed frequency systems". United States. https://www.osti.gov/servlets/purl/874076.
@article{osti_874076,
title = {Wide tracking range, auto ranging, low jitter phase lock loop for swept and fixed frequency systems},
author = {Kerner, Thomas M},
abstractNote = {The present invention provides a wide tracking range phase locked loop (PLL) circuit that achieves minimal jitter in a recovered clock signal, regardless of the source of the jitter (i.e. whether it is in the source or the transmission media). The present invention PLL has automatic harmonic lockout detection circuitry via a novel lock and seek control logic in electrical communication with a programmable frequency discriminator and a code balance detector. (The frequency discriminator enables preset of a frequency window of upper and lower frequency limits to derive a programmable range within which signal acquisition is effected. The discriminator works in combination with the code balance detector circuit to minimize the sensitivity of the PLL circuit to random data in the data stream). In addition, the combination of a differential loop integrator with the lock and seek control logic obviates a code preamble and guarantees signal acquisition without harmonic lockup. An adaptive cable equalizer is desirably used in combination with the present invention PLL to recover encoded transmissions containing a clock and/or data. The equalizer automatically adapts to equalize short haul cable lengths of coaxial and twisted pair cables or wires and provides superior jitter performance itself. The combination of the equalizer with the present invention PLL is desirable in that such combination permits the use of short haul wires without significant jitter.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Mon Jan 01 00:00:00 EST 2001},
month = {Mon Jan 01 00:00:00 EST 2001}
}