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Title: Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

Abstract

A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

Inventors:
 [1];  [1];  [1];  [2]
  1. (Albuquerque, NM)
  2. (Tijeras, NM)
Issue Date:
Research Org.:
SANDIA CORP
OSTI Identifier:
873901
Patent Number(s):
6268630
Assignee:
Sandia Corporation (Albuquerque, NM) SNL
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
silicon-on-insulator; field; effect; transistor; improved; ties; rad-hard; applications; soi; field-effect; fet; method; disclosed; characterized; source; extends; partially; half-way; active; layer; formed; additionally; minimal-area; tie; contact; provided; short-circuit; electrical; connection; reducing; floating; effects; improves; characteristics; provides; single-event-upset; seu; radiation; hardness; device; terrestrial; space; improvement; total-dose; compared; conventional; transistors; fabricated; specially; prepared; hardened; buried; oxide; complementary; n-channel; p-channel; fets; according; form; integrated; circuits; ics; commercial; military; space applications; buried oxide; field-effect transistor; field effect; integrated circuits; integrated circuit; oxide layer; electrical connection; active layer; electrical characteristics; effect transistor; radiation hard; radiation hardness; specially prepared; fabricated according; electrical characteristic; /257/

Citation Formats

Schwank, James R., Shaneyfelt, Marty R., Draper, Bruce L., and Dodd, Paul E. Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications. United States: N. p., 2001. Web.
Schwank, James R., Shaneyfelt, Marty R., Draper, Bruce L., & Dodd, Paul E. Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications. United States.
Schwank, James R., Shaneyfelt, Marty R., Draper, Bruce L., and Dodd, Paul E. Mon . "Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications". United States. https://www.osti.gov/servlets/purl/873901.
@article{osti_873901,
title = {Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications},
author = {Schwank, James R. and Shaneyfelt, Marty R. and Draper, Bruce L. and Dodd, Paul E.},
abstractNote = {A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2001},
month = {1}
}

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