Title: Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer

Abstract

A method for screening or qualifying semiconductor substrates for integrated circuit fabrication. The method comprises the steps of annealing at least one semiconductor substrate at a first temperature in a defect-activating ambient (e.g. hydrogen, forming gas, or ammonia) for sufficient time for activating any defects within on oxide layer of the substrate; measuring a defect-revealing electrical characteristic of at least a portion of the oxide layer for determining a quantity of activated defects therein; and selecting substrates for which the quantity of activated defects is below a predetermined level. The defect-revealing electrical characteristic may be a capacitance-versus-voltage (C-V) characteristic or a current-versus-voltage (I-V) characteristic that is dependent on an electrical charge in the oxide layer generated by the activated defects. Embodiments of the present invention may be applied for screening any type of semiconductor substrate or wafer having an oxide layer formed thereon or therein. This includes silicon-on-insulator substrates formed by a separation by the implantation of oxygen (SIMOX) process or the bond and etch back silicon-on-insulator (BESOI) process, as well as silicon substrates having a thermal oxide layer or a deposited oxide layer.

Inventors:

Warren, William L ^[1]; Vanheusden, Karel J. R. ^[1]; Schwank, James R ^[1]; Fleetwood, Daniel M ^[1]; Shaneyfelt, Marty R ^[1]; Winokur, Peter S ^[1]; Devine, Roderick A. B. ^[2]

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+ Show Inventor Affiliations

1. Albuquerque, NM
2. St. Martin le Vinoux, FR

Issue Date:

Tue Jul 28 00:00:00 EDT 1998

Research Org.:

Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)

OSTI Identifier:

871740

Patent Number(s):

5786231

Assignee:

Sandia Corporation (Albuquerque, NM)

Patent Classifications (CPCs):

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

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H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

H01L22/14 - {for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means}
H01L22/20 - {Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps}

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DOE Contract Number:  

AC04-94AL85000

Resource Type:

Patent

Country of Publication:

United States

Language:

English

Subject:

screening; method; selecting; semiconductor; substrates; defects; below; predetermined; level; oxide; layer; qualifying; integrated; circuit; fabrication; comprises; steps; annealing; substrate; temperature; defect-activating; ambient; hydrogen; forming; gas; ammonia; sufficient; time; activating; measuring; defect-revealing; electrical; characteristic; portion; determining; quantity; activated; therein; capacitance-versus-voltage; c-v; current-versus-voltage; i-v; dependent; charge; generated; embodiments; applied; type; wafer; formed; thereon; silicon-on-insulator; separation; implantation; oxygen; simox; process; bond; etch; besoi; silicon; thermal; deposited; circuit fabrication; forming gas; electrical charge; silicon substrates; layer formed; semiconductor substrate; method comprises; silicon substrate; integrated circuit; oxide layer; sufficient time; predetermined level; formed thereon; semiconductor substrates; substrates formed; method comprise; insulator substrate; defects therein; electrical characteristic; /438/324/