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Title: Repairable chip bonding/interconnect process

A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.
 [1];  [2];  [2];  [3]
  1. (Berkeley, CA)
  2. (Livermore, CA)
  3. (Tracy, CA)
Issue Date:
OSTI Identifier:
Regents of University of California (Oakland, CA) LLNL
Patent Number(s):
US 5653019
Contract Number:
Research Org:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Country of Publication:
United States
repairable; chip; bonding; interconnect; process; chip-to-board; addresses; cost; testability; issues; multi-chip; modules; carried; chip-on-sacrificial-substrate; technique; involving; laser; processing; avoids; curing; solvent; evolution; encountered; prior; approaches; resolving; plating; requirements; fillets; speed; connection; transmission; lines; formed; bond; pads; gull; bottom; subsequent; solder; multi-chip modules; transmission lines; transmission line; bond pads; laser processing; multi-chip module; chip bond; interconnect process; /29/257/438/