Method of pedestal and common-mode noise correction for switched-capacitor analog memories

Title: Method of pedestal and common-mode noise correction for switched-capacitor analog memories

Full Record
Other Related Research

Abstract

A method and apparatus for correcting common-mode noise and pedestal noise in a multichannel array of switched-capacitor analog memories wherein each analog memory is connected to an associated analog-to-digital converter. The apparatus comprises a single differential element in two different embodiments. In a first embodiment, the differential element is a reference analog memory connected to a buffer. In the second embodiment, the differential element is a reference analog memory connected to a reference analog-to-digital connected to an array of digital summing circuits.

Inventors:

Britton, Charles L ^[1]

Alcoa, TN

Issue Date:: 1996-01-01

Research Org.:: Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)

OSTI Identifier:: 870764

Patent Number(s):: 5590104

Assignee:: Martin Marietta Energy Systems, Inc. (Oak Ridge, TN)

Patent Classifications (CPCs):: G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES

Show more

G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
G11C27/00 - Electric analogue stores, e.g. for storing instantaneous values {

Show less

DOE Contract Number:: AC05-84OR21400

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: method; pedestal; common-mode; noise; correction; switched-capacitor; analog; memories; apparatus; correcting; multichannel; array; memory; connected; associated; analog-to-digital; converter; comprises; single; differential; element; embodiments; embodiment; reference; buffer; digital; summing; circuits; analog memory; analog-to-digital converter; apparatus comprises; apparatus comprise; switched-capacitor analog; common-mode noise; analog memories; multichannel array; pedestal noise; noise correction; digital converter; correcting common-mode; /365/

Citation Formats


                    Britton, Charles L. Method of pedestal and common-mode noise correction for switched-capacitor analog memories.  United States: N. p., 1996. 
        Web.

Copy to clipboard


                    Britton, Charles L. Method of pedestal and common-mode noise correction for switched-capacitor analog memories.  United States.

Copy to clipboard


                    Britton, Charles L. Mon .  
        "Method of pedestal and common-mode noise correction for switched-capacitor analog memories".  United States.  https://www.osti.gov/servlets/purl/870764.

Copy to clipboard


                    
@article{osti_870764,

  title        = {Method of pedestal and common-mode noise correction for switched-capacitor analog memories},

  author       = {Britton, Charles L},

  abstractNote = {A method and apparatus for correcting common-mode noise and pedestal noise in a multichannel array of switched-capacitor analog memories wherein each analog memory is connected to an associated analog-to-digital converter. The apparatus comprises a single differential element in two different embodiments. In a first embodiment, the differential element is a reference analog memory connected to a buffer. In the second embodiment, the differential element is a reference analog memory connected to a reference analog-to-digital connected to an array of digital summing circuits.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {1996},

  month        = {1}

}

Copy to clipboard

Patent:

View Patent

Save / Share:

Export Metadata

Save to My Library

Similar Records in DOE Patents and OSTI.GOV collections:

Method of pedestal and common-mode noise correction for switched-capacitor analog memories

Patent Britton, Charles L [Alcoa, TN]

A method and apparatus for correcting common-mode noise and pedestal noise in a multichannel array of switched-capacitor analog memories wherein each analog memory is connected to an associated analog-to-digital converter. The apparatus comprises a single differential element in two different embodiments. In a first embodiment, the differential element is a reference analog memory connected to a buffer. In the second embodiment, the differential dement is a reference analog memory connected to a reference analog-to-digital connected to an array of digital summing circuits.
Full Text Available
Method of pedestal and common-mode noise correction for switched-capacitor analog memories

Patent Britton, C L

A method and apparatus are disclosed for correcting common-mode noise and pedestal noise in a multichannel array of switched-capacitor analog memories wherein each analog memory is connected to an associated analog-to-digital converter. The apparatus comprises a single differential element in two different embodiments. In a first embodiment, the differential element is a reference analog memory connected to a buffer. In the second embodiment, the differential element is a reference analog memory connected to a reference analog-to-digital connected to an array of digital summing circuits. 4 figs.
Method of pedestal and common-mode noise correction for switched-capacitor analog memories

Patent Britton, C L

A method and apparatus are disclosed for correcting common-mode noise and pedestal noise in a multichannel array of switched-capacitor analog memories wherein each analog memory is connected to an associated analog-to-digital converter. The apparatus comprises a single differential element in two different embodiments. In a first embodiment, the differential element is a reference analog memory connected to a buffer. In the second embodiment, the differential dement is a reference analog memory connected to a reference analog-to-digital connected to an array of digital summing circuits. 4 figs.
Device and methods for writing and erasing analog information in small memory units via voltage pulses

Patent El Gabaly Marquez, Farid; Talin, Albert Alec

Devices and methods for non-volatile analog data storage are described herein. In an exemplary embodiment, an analog memory device comprises a potential-carrier source layer, a barrier layer deposited on the source layer, and at least two storage layers deposited on the barrier layer. The memory device can be prepared to write and read data via application of a biasing voltage between the source layer and the storage layers, wherein the biasing voltage causes potential-carriers to migrate into the storage layers. After initialization, data can be written to the memory device by application of a voltage pulse between two storage layersmore »« less
Full Text Available
Time-mode analog computation circuits and methods

Patent Ravinuthula, Vishnu V.; Harris, John G.; Fortes, Jose A. B.

A time-mode analog computation circuit is provided. The time-mode analog computation circuit includes one or more inputs for receiving one or more temporal input signals. The time-mode analog computation circuit further includes circuitry for performing a mathematical operation based on the one or more temporal input signals. A result of the mathematical operation is expressed in a timing of an output signal generated by the circuit.
Full Text Available

Similar Records