Multidimensional spectral load balancing
Abstract
A method of and apparatus for graph partitioning involving the use of a plurality of eigenvectors of the Laplacian matrix of the graph of the problem for which load balancing is desired. The invention is particularly useful for optimizing parallel computer processing of a problem and for minimizing total pathway lengths of integrated circuits in the design stage.
- Inventors:
-
- Albuquerque, NM
- Issue Date:
- Research Org.:
- Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
- OSTI Identifier:
- 870755
- Patent Number(s):
- 5587922
- Application Number:
- 08/680,718
- Assignee:
- Sandia Corporation (Albuquerque, NM)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- multidimensional; spectral; load; balancing; method; apparatus; graph; partitioning; involving; plurality; eigenvectors; laplacian; matrix; desired; particularly; useful; optimizing; parallel; computer; processing; minimizing; total; pathway; lengths; integrated; circuits; design; stage; load balancing; particularly useful; integrated circuits; integrated circuit; parallel computer; computer process; /716/712/
Citation Formats
Hendrickson, Bruce A, and Leland, Robert W. Multidimensional spectral load balancing. United States: N. p., 1996.
Web.
Hendrickson, Bruce A, & Leland, Robert W. Multidimensional spectral load balancing. United States.
Hendrickson, Bruce A, and Leland, Robert W. Mon .
"Multidimensional spectral load balancing". United States. https://www.osti.gov/servlets/purl/870755.
@article{osti_870755,
title = {Multidimensional spectral load balancing},
author = {Hendrickson, Bruce A and Leland, Robert W},
abstractNote = {A method of and apparatus for graph partitioning involving the use of a plurality of eigenvectors of the Laplacian matrix of the graph of the problem for which load balancing is desired. The invention is particularly useful for optimizing parallel computer processing of a problem and for minimizing total pathway lengths of integrated circuits in the design stage.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1996},
month = {1}
}
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