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Title: High-performance parallel interface to synchronous optical network gateway

A system of sending and receiving gateways interconnects high speed data interfaces, e.g., HIPPI interfaces, through fiber optic links, e.g., a SONET network. An electronic stripe distributor distributes bytes of data from a first interface at the sending gateway onto parallel fiber optics of the fiber optic link to form transmitted data. An electronic stripe collector receives the transmitted data on the parallel fiber optics and reforms the data into a format effective for input to a second interface at the receiving gateway. Preferably, an error correcting syndrome is constructed at the sending gateway and sent with a data frame so that transmission errors can be detected and corrected in a real-time basis. Since the high speed data interface operates faster than any of the fiber optic links the transmission rate must be adapted to match the available number of fiber optic links so the sending and receiving gateways monitor the availability of fiber links and adjust the data throughput accordingly. In another aspect, the receiving gateway must have sufficient available buffer capacity to accept an incoming data frame. A credit-based flow control system provides for continuously updating the sending gateway on the available buffer capacity at the receiving gateway.
 [1];  [1]
  1. (Los Alamos, NM)
Issue Date:
OSTI Identifier:
Regents of Univ. of California Office of Technology Transfer (Alameda, CA) LANL
Patent Number(s):
US 5581566
Contract Number:
Research Org:
Los Alamos National Laboratory (LANL), Los Alamos, NM
Country of Publication:
United States
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