Title: Method for shallow junction formation

Abstract

A doping sequence that reduces the cost and complexity of forming source/drain regions in complementary metal oxide silicon (CMOS) integrated circuit technologies. The process combines the use of patterned excimer laser annealing, dopant-saturated spin-on glass, silicide contact structures and interference effects creates by thin dielectric layers to produce source and drain junctions that are ultrashallow in depth but exhibit low sheet and contact resistance. The process utilizes no photolithography and can be achieved without the use of expensive vacuum equipment. The process margins are wide, and yield loss due to contact of the ultrashallow dopants is eliminated.

Inventors:

Weiner, Kurt H ^[1]

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+ Show Inventor Affiliations

1. San Jose, CA

Issue Date:

Mon Jan 01 00:00:00 EST 1996

Research Org.:

Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

OSTI Identifier:

870664

Patent Number(s):

5569624

Assignee:

Regents of University of California (Oakland, CA)

Patent Classifications (CPCs):

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC Y10S - TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

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H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

H01L21/2255 - {the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides}
H01L21/2257 - {the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon}
H01L21/823814 - {with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures}
H01L29/6659 - {with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET}

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC Y10S - TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

Y10S148/09 - Laser anneal
Y10S438/923 - Diffusion through a layer

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DOE Contract Number:  

W-7405-ENG-48

Resource Type:

Patent

Country of Publication:

United States

Language:

English

Subject:

method; shallow; junction; formation; doping; sequence; reduces; cost; complexity; forming; source; drain; regions; complementary; metal; oxide; silicon; cmos; integrated; circuit; technologies; process; combines; patterned; excimer; laser; annealing; dopant-saturated; spin-on; glass; silicide; contact; structures; interference; effects; creates; dielectric; layers; produce; junctions; ultrashallow; depth; exhibit; sheet; resistance; utilizes; photolithography; achieved; expensive; vacuum; equipment; margins; wide; yield; loss; due; dopants; eliminated; dielectric layers; laser annealing; process utilizes; dielectric layer; metal oxide; integrated circuit; contact resistance; excimer laser; spin-on glass; shallow junction; complementary metal; contact structure; interference effect; process combines; contact structures; junction formation; /438/148/