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Title: High speed imager test station

Abstract

A test station enables the performance of a solid state imager (herein called a focal plane array or FPA) to be determined at high image frame rates. A programmable waveform generator is adapted to generate clock pulses at determinable rates for clock light-induced charges from a FPA. The FPA is mounted on an imager header board for placing the imager in operable proximity to level shifters for receiving the clock pulses and outputting pulses effective to clock charge from the pixels forming the FPA. Each of the clock level shifters is driven by leading and trailing edge portions of the clock pulses to reduce power dissipation in the FPA. Analog circuits receive output charge pulses clocked from the FPA pixels. The analog circuits condition the charge pulses to cancel noise in the pulses and to determine and hold a peak value of the charge for digitizing. A high speed digitizer receives the peak signal value and outputs a digital representation of each one of the charge pulses. A video system then displays an image associated with the digital representation of the output charge pulses clocked from the FPA. In one embodiment, the FPA image is formatted to a standard videomore » format for display on conventional video equipment.« less

Inventors:
 [1];  [2];  [3]
  1. (Santa Fe, NM)
  2. (Los Alamos, NM)
  3. (Moraga, CA)
Issue Date:
Research Org.:
Los Alamos National Laboratory (LANL), Los Alamos, NM
OSTI Identifier:
870158
Patent Number(s):
5467128
Assignee:
Regents of University of California, Office of Technology (Alameda, CA) LANL
DOE Contract Number:  
W-7405-ENG-36
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
speed; imager; station; enables; performance; solid; called; focal; plane; array; fpa; determined; image; frame; rates; programmable; waveform; generator; adapted; generate; clock; pulses; determinable; light-induced; charges; mounted; header; board; placing; operable; proximity; level; shifters; receiving; outputting; effective; charge; pixels; forming; driven; leading; trailing; edge; portions; reduce; power; dissipation; analog; circuits; receive; output; clocked; condition; cancel; noise; determine; hold; peak; value; digitizing; digitizer; receives; signal; outputs; digital; representation; video; displays; associated; embodiment; formatted; standard; format; display; conventional; equipment; plane array; charge pulses; edge portions; power dissipation; clock pulse; trailing edge; focal plane; waveform generator; clock pulses; edge portion; peak value; output charge; standard video; reduce power; analog circuit; digital representation; signal value; video format; speed digitizer; programmable waveform; /348/702/

Citation Formats

Yates, George J., Albright, Kevin L., and Turko, Bojan T. High speed imager test station. United States: N. p., 1995. Web.
Yates, George J., Albright, Kevin L., & Turko, Bojan T. High speed imager test station. United States.
Yates, George J., Albright, Kevin L., and Turko, Bojan T. Sun . "High speed imager test station". United States. https://www.osti.gov/servlets/purl/870158.
@article{osti_870158,
title = {High speed imager test station},
author = {Yates, George J. and Albright, Kevin L. and Turko, Bojan T.},
abstractNote = {A test station enables the performance of a solid state imager (herein called a focal plane array or FPA) to be determined at high image frame rates. A programmable waveform generator is adapted to generate clock pulses at determinable rates for clock light-induced charges from a FPA. The FPA is mounted on an imager header board for placing the imager in operable proximity to level shifters for receiving the clock pulses and outputting pulses effective to clock charge from the pixels forming the FPA. Each of the clock level shifters is driven by leading and trailing edge portions of the clock pulses to reduce power dissipation in the FPA. Analog circuits receive output charge pulses clocked from the FPA pixels. The analog circuits condition the charge pulses to cancel noise in the pulses and to determine and hold a peak value of the charge for digitizing. A high speed digitizer receives the peak signal value and outputs a digital representation of each one of the charge pulses. A video system then displays an image associated with the digital representation of the output charge pulses clocked from the FPA. In one embodiment, the FPA image is formatted to a standard video format for display on conventional video equipment.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1995},
month = {1}
}

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