High performance static latches with complete single event upset immunity
Abstract
An asymmetric response latch providing immunity to single event upset without loss of speed. The latch has cross-coupled inverters having a hardened logic state and a soft state, wherein the logic state of the first inverter can only be changed when the voltage on the coupling node of that inverter is low and the logic state of the second inverter can only be changed when the coupling of that inverter is high. One of more of the asymmetric response latches may be configured into a memory cell having complete immunity, which protects information rather than logic states.
- Inventors:
-
- Albuquerque, NM
- Issue Date:
- Research Org.:
- AT&T
- OSTI Identifier:
- 869264
- Patent Number(s):
- 5307142
- Assignee:
- United States of America as represented by United States (Washington, DC)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G - PHYSICS G11 - INFORMATION STORAGE G11C - STATIC STORES
- DOE Contract Number:
- AC04-76DP00789
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- performance; static; latches; complete; single; event; upset; immunity; asymmetric; response; latch; providing; loss; speed; cross-coupled; inverters; hardened; logic; soft; inverter; changed; voltage; coupling; node; configured; memory; cell; protects; information; single event; memory cell; event upset; static latch; /365/714/
Citation Formats
Corbett, Wayne T, and Weaver, Harry T. High performance static latches with complete single event upset immunity. United States: N. p., 1994.
Web.
Corbett, Wayne T, & Weaver, Harry T. High performance static latches with complete single event upset immunity. United States.
Corbett, Wayne T, and Weaver, Harry T. Sat .
"High performance static latches with complete single event upset immunity". United States. https://www.osti.gov/servlets/purl/869264.
@article{osti_869264,
title = {High performance static latches with complete single event upset immunity},
author = {Corbett, Wayne T and Weaver, Harry T},
abstractNote = {An asymmetric response latch providing immunity to single event upset without loss of speed. The latch has cross-coupled inverters having a hardened logic state and a soft state, wherein the logic state of the first inverter can only be changed when the voltage on the coupling node of that inverter is low and the logic state of the second inverter can only be changed when the coupling of that inverter is high. One of more of the asymmetric response latches may be configured into a memory cell having complete immunity, which protects information rather than logic states.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1994},
month = {1}
}
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