Electrochemical planarization
Abstract
In a process for fabricating planarized thin film metal interconnects for integrated circuit structures, a planarized metal layer is etched back to the underlying dielectric layer by electropolishing, ion milling or other procedure. Electropolishing reduces processing time from hours to minutes and allows batch processing of multiple wafers. The etched back planarized thin film interconnect is flush with the dielectric layer.
- Inventors:
-
- Berkeley, CA
- Pleasanton, CA
- Issue Date:
- Research Org.:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- OSTI Identifier:
- 868983
- Patent Number(s):
- 5256565
- Assignee:
- United States of America as represented by United States (Washington, DC)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
- DOE Contract Number:
- W-7405-ENG-48
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- electrochemical; planarization; process; fabricating; planarized; film; metal; interconnects; integrated; circuit; structures; layer; etched; underlying; dielectric; electropolishing; milling; procedure; reduces; processing; time; hours; minutes; allows; batch; multiple; wafers; interconnect; flush; processing time; dielectric layer; metal layer; integrated circuit; multiple wafers; batch processing; batch process; film metal; circuit structure; /438/205/
Citation Formats
Bernhardt, Anthony F, and Contolini, Robert J. Electrochemical planarization. United States: N. p., 1993.
Web.
Bernhardt, Anthony F, & Contolini, Robert J. Electrochemical planarization. United States.
Bernhardt, Anthony F, and Contolini, Robert J. Fri .
"Electrochemical planarization". United States. https://www.osti.gov/servlets/purl/868983.
@article{osti_868983,
title = {Electrochemical planarization},
author = {Bernhardt, Anthony F and Contolini, Robert J},
abstractNote = {In a process for fabricating planarized thin film metal interconnects for integrated circuit structures, a planarized metal layer is etched back to the underlying dielectric layer by electropolishing, ion milling or other procedure. Electropolishing reduces processing time from hours to minutes and allows batch processing of multiple wafers. The etched back planarized thin film interconnect is flush with the dielectric layer.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Fri Jan 01 00:00:00 EST 1993},
month = {Fri Jan 01 00:00:00 EST 1993}
}
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