Title: Method for reducing or eliminating interface defects in mismatched semiconductor epilayers

Abstract

The present invention and process relates to crystal lattice mismatched semiconductor composite having a first semiconductor layer and a second semiconductor growth layer deposited thereon to form an interface wherein the growth layer can be deposited at thicknesses in excess of the critical thickness, even up to about 10.times. critical thickness. Such composite has an interface which is substantially free of interface defects. For example, the size of the growth areas in a mismatched In.sub.0.05 Ga.sub.0.95 As/(001)GaAs interface was controlled by fabricating 2-.mu.m high pillars of various lateral geometries and lateral dimensions before the epitaxial deposition of 3500.ANG. of In.sub.0.05 Ga.sub.0.95 As. The linear dislocation density at the interface was reduced from >5000 dislocations/cm to about zero for 25-.mu.m lateral dimensions and to less than 800 dislocations/cm for lateral dimensions as large as 100 .mu.m. The fabricated pillars control the lateral dimensions of the growth layer and block the glide of misfit dislocations with the resultant decrease in dislocation density.

Inventors:

Fitzgerald, Jr., Eugene A. ^[1]; Ast, Dieter G ^[2]

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+ Show Inventor Affiliations

1. (Ithaca, NY)
2. Ithaca, NY

Issue Date:

1992-01-01

Research Org.:

Cornell Univ., Ithaca, NY (United States)

OSTI Identifier:

868507

Patent Number(s):

5156995

Assignee:

Cornell Research Foundation, Inc. (Ithaca, NY)

Patent Classifications (CPCs):

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC Y10S - TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

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H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

H01L21/02381 - {Silicon, silicon germanium, germanium}
H01L21/02395 - {Arsenides}
H01L21/0243 - {Surface structure}
H01L21/02463 - {Arsenides}
H01L21/02532 - {Silicon, silicon germanium, germanium}
H01L21/02546 - {Arsenides}
H01L21/0256 - {Selenides}
H01L21/02658 - {Pretreatments
H01L29/205 - in different semiconductor regions {, e.g. heterojunctions}
H01L29/225 - in different semiconductor regions {, e.g. heterojunctions}
H01L29/26 - including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24 {, e.g. alloys}

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC Y10S - TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

Y10S438/933 - Germanium or silicon or Ge-Si on III-V
Y10S438/938 - Lattice strain control or utilization

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DOE Contract Number:  

FG02-86ER45278

Resource Type:

Patent

Country of Publication:

United States

Language:

English

Subject:

method; reducing; eliminating; interface; defects; mismatched; semiconductor; epilayers; process; relates; crystal; lattice; composite; layer; growth; deposited; thereon; form; thicknesses; excess; critical; thickness; 10; times; substantially; free; example; size; 05; 95; 001; gaas; controlled; fabricating; 2-; pillars; various; lateral; geometries; dimensions; epitaxial; deposition; 3500; ang; linear; dislocation; density; reduced; 5000; dislocations; cm; zero; 25-; 800; 100; fabricated; control; block; glide; misfit; resultant; decrease; substantially free; semiconductor layer; deposited thereon; layer deposited; crystal lattice; lateral dimensions; process relates; mismatched semiconductor; dislocation density; interface defects; semiconductor epilayers; semiconductor growth; semiconductor composite; epitaxial deposition; lattice mismatch; eliminating interface; semiconductor epilayer; lattice mismatched; /438/