skip to main content
DOE Patents title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Method for reducing or eliminating interface defects in mismatched semiconductor epilayers

Abstract

The present invention and process relates to crystal lattice mismatched semiconductor composite having a first semiconductor layer and a second semiconductor growth layer deposited thereon to form an interface wherein the growth layer can be deposited at thicknesses in excess of the critical thickness, even up to about 10.times. critical thickness. Such composite has an interface which is substantially free of interface defects. For example, the size of the growth areas in a mismatched In.sub.0.05 Ga.sub.0.95 As/(001)GaAs interface was controlled by fabricating 2-.mu.m high pillars of various lateral geometries and lateral dimensions before the epitaxial deposition of 3500.ANG. of In.sub.0.05 Ga.sub.0.95 As. The linear dislocation density at the interface was reduced from >5000 dislocations/cm to about zero for 25-.mu.m lateral dimensions and to less than 800 dislocations/cm for lateral dimensions as large as 100 .mu.m. The fabricated pillars control the lateral dimensions of the growth layer and block the glide of misfit dislocations with the resultant decrease in dislocation density.

Inventors:
 [1];  [2]
  1. (Ithaca, NY)
  2. Ithaca, NY
Issue Date:
Research Org.:
Cornell Univ., Ithaca, NY (United States)
OSTI Identifier:
868507
Patent Number(s):
5156995
Assignee:
Cornell Research Foundation, Inc. (Ithaca, NY)
Patent Classifications (CPCs):
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC Y10S - TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
DOE Contract Number:  
FG02-86ER45278
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
method; reducing; eliminating; interface; defects; mismatched; semiconductor; epilayers; process; relates; crystal; lattice; composite; layer; growth; deposited; thereon; form; thicknesses; excess; critical; thickness; 10; times; substantially; free; example; size; 05; 95; 001; gaas; controlled; fabricating; 2-; pillars; various; lateral; geometries; dimensions; epitaxial; deposition; 3500; ang; linear; dislocation; density; reduced; 5000; dislocations; cm; zero; 25-; 800; 100; fabricated; control; block; glide; misfit; resultant; decrease; substantially free; semiconductor layer; deposited thereon; layer deposited; crystal lattice; lateral dimensions; process relates; mismatched semiconductor; dislocation density; interface defects; semiconductor epilayers; semiconductor growth; semiconductor composite; epitaxial deposition; lattice mismatch; eliminating interface; semiconductor epilayer; lattice mismatched; /438/

Citation Formats

Fitzgerald, Jr., Eugene A., and Ast, Dieter G. Method for reducing or eliminating interface defects in mismatched semiconductor epilayers. United States: N. p., 1992. Web.
Fitzgerald, Jr., Eugene A., & Ast, Dieter G. Method for reducing or eliminating interface defects in mismatched semiconductor epilayers. United States.
Fitzgerald, Jr., Eugene A., and Ast, Dieter G. Wed . "Method for reducing or eliminating interface defects in mismatched semiconductor epilayers". United States. https://www.osti.gov/servlets/purl/868507.
@article{osti_868507,
title = {Method for reducing or eliminating interface defects in mismatched semiconductor epilayers},
author = {Fitzgerald, Jr., Eugene A. and Ast, Dieter G},
abstractNote = {The present invention and process relates to crystal lattice mismatched semiconductor composite having a first semiconductor layer and a second semiconductor growth layer deposited thereon to form an interface wherein the growth layer can be deposited at thicknesses in excess of the critical thickness, even up to about 10.times. critical thickness. Such composite has an interface which is substantially free of interface defects. For example, the size of the growth areas in a mismatched In.sub.0.05 Ga.sub.0.95 As/(001)GaAs interface was controlled by fabricating 2-.mu.m high pillars of various lateral geometries and lateral dimensions before the epitaxial deposition of 3500.ANG. of In.sub.0.05 Ga.sub.0.95 As. The linear dislocation density at the interface was reduced from >5000 dislocations/cm to about zero for 25-.mu.m lateral dimensions and to less than 800 dislocations/cm for lateral dimensions as large as 100 .mu.m. The fabricated pillars control the lateral dimensions of the growth layer and block the glide of misfit dislocations with the resultant decrease in dislocation density.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1992},
month = {1}
}

Patent:

Save / Share: