Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system
Abstract
A bus switching apparatus and method for multiple processor computer systems comprises a plurality of bus switches interconnected by branch buses. Each processor or other module of the system is connected to a spigot of a bus switch. Each bus switch also serves as part of a backplane of a modular crate hardware package. A processor initiates communication with another processor by identifying that other processor. The bus switch to which the initiating processor is connected identifies and secures, if possible, a path to that other processor, either directly or via one or more other bus switches which operate similarly. If a particular desired path through a given bus switch is not available to be used, an alternate path is considered, identified and secured.
- Inventors:
-
- Aurora, IL
- Warrenville, IL
- DeKalb, IL
- Issue Date:
- Research Org.:
- Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States)
- OSTI Identifier:
- 867678
- Patent Number(s):
- 4985830
- Assignee:
- Universities Research Association, Inc. (Washington, DC)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- AC02-76CH03000
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- interprocessor; bus; switching; simultaneous; communication; plural; parallel; processing; apparatus; method; multiple; processor; computer; systems; comprises; plurality; switches; interconnected; branch; buses; module; connected; spigot; switch; serves; backplane; modular; crate; hardware; package; initiates; identifying; initiating; identifies; secures; path; directly; via; operate; similarly; particular; desired; available; alternate; considered; identified; secured; computer systems; parallel processing; bus switch; systems comprises; parallel process; systems comprise; bus switching; processor computer; /709/370/710/
Citation Formats
Atac, Robert, Fischler, Mark S, and Husby, Donald E. Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system. United States: N. p., 1991.
Web.
Atac, Robert, Fischler, Mark S, & Husby, Donald E. Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system. United States.
Atac, Robert, Fischler, Mark S, and Husby, Donald E. Tue .
"Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system". United States. https://www.osti.gov/servlets/purl/867678.
@article{osti_867678,
title = {Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system},
author = {Atac, Robert and Fischler, Mark S and Husby, Donald E},
abstractNote = {A bus switching apparatus and method for multiple processor computer systems comprises a plurality of bus switches interconnected by branch buses. Each processor or other module of the system is connected to a spigot of a bus switch. Each bus switch also serves as part of a backplane of a modular crate hardware package. A processor initiates communication with another processor by identifying that other processor. The bus switch to which the initiating processor is connected identifies and secures, if possible, a path to that other processor, either directly or via one or more other bus switches which operate similarly. If a particular desired path through a given bus switch is not available to be used, an alternate path is considered, identified and secured.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Jan 01 00:00:00 EST 1991},
month = {Tue Jan 01 00:00:00 EST 1991}
}