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Title: Multiple channel data acquisition system

Abstract

A multiple channel data acquisition system for the transfer of large amounts of data from a multiplicity of data channels has a plurality of modules which operate in parallel to convert analog signals to digital data and transfer that data to a communications host via a FASTBUS. Each module has a plurality of submodules which include a front end buffer (FEB) connected to input circuitry having an analog to digital converter with cache memory for each of a plurality of channels. The submodules are interfaced with the FASTBUS via a FASTBUS coupler which controls a module bus and a module memory. The system is triggered to effect rapid parallel data samplings which are stored to the cache memories. The cache memories are uploaded to the FEBs during which zero suppression occurs. The data in the FEBs is reformatted and compressed by a local processor during transfer to the module memory. The FASTBUS coupler is used by the communications host to upload the compressed and formatted data from the module memory. The local processor executes programs which are downloaded to the module memory through the FASTBUS coupler.

Inventors:
 [1];  [1];  [1];  [1];  [2];  [1];  [3]
  1. Ames, IA
  2. Boone, IA
  3. (Ames, IA)
Issue Date:
Research Org.:
Ames Laboratory (AMES), Ames, IA; Iowa State University, Ames, IA (US)
OSTI Identifier:
867400
Patent Number(s):
4928246
Application Number:
07/261,031
Assignee:
Iowa State University Research Foundation, Inc. (Ames, IA)
DOE Contract Number:  
W-7405-ENG-82
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
multiple; channel; data; acquisition; transfer; amounts; multiplicity; channels; plurality; modules; operate; parallel; convert; analog; signals; digital; communications; host; via; fastbus; module; submodules; front; buffer; feb; connected; input; circuitry; converter; cache; memory; interfaced; coupler; controls; bus; triggered; effect; rapid; samplings; stored; memories; uploaded; febs; zero; suppression; occurs; reformatted; compressed; local; processor; upload; formatted; executes; programs; downloaded; digital data; multiple channel; data acquisition; analog signal; channel data; analog signals; parallel data; digital converter; /700/340/341/

Citation Formats

Crawley, H Bert, Rosenberg, Eli I, Meyer, W Thomas, Gorbics, Mark S, Thomas, William D, McKay, Roy L, and Homer, Jr., John F. Multiple channel data acquisition system. United States: N. p., 1990. Web.
Crawley, H Bert, Rosenberg, Eli I, Meyer, W Thomas, Gorbics, Mark S, Thomas, William D, McKay, Roy L, & Homer, Jr., John F. Multiple channel data acquisition system. United States.
Crawley, H Bert, Rosenberg, Eli I, Meyer, W Thomas, Gorbics, Mark S, Thomas, William D, McKay, Roy L, and Homer, Jr., John F. Tue . "Multiple channel data acquisition system". United States. https://www.osti.gov/servlets/purl/867400.
@article{osti_867400,
title = {Multiple channel data acquisition system},
author = {Crawley, H Bert and Rosenberg, Eli I and Meyer, W Thomas and Gorbics, Mark S and Thomas, William D and McKay, Roy L and Homer, Jr., John F.},
abstractNote = {A multiple channel data acquisition system for the transfer of large amounts of data from a multiplicity of data channels has a plurality of modules which operate in parallel to convert analog signals to digital data and transfer that data to a communications host via a FASTBUS. Each module has a plurality of submodules which include a front end buffer (FEB) connected to input circuitry having an analog to digital converter with cache memory for each of a plurality of channels. The submodules are interfaced with the FASTBUS via a FASTBUS coupler which controls a module bus and a module memory. The system is triggered to effect rapid parallel data samplings which are stored to the cache memories. The cache memories are uploaded to the FEBs during which zero suppression occurs. The data in the FEBs is reformatted and compressed by a local processor during transfer to the module memory. The FASTBUS coupler is used by the communications host to upload the compressed and formatted data from the module memory. The local processor executes programs which are downloaded to the module memory through the FASTBUS coupler.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1990},
month = {5}
}

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