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Title: Multi-processor including data flow accelerator module

Abstract

An accelerator module for a data flow computer includes an intelligent memory. The module is added to a multiprocessor arrangement and uses a shared tagged memory architecture in the data flow computer. The intelligent memory module assigns locations for holding data values in correspondence with arcs leading to a node in a data dependency graph. Each primitive computation is associated with a corresponding memory cell, including a number of slots for operands needed to execute a primitive computation, a primitive identifying pointer, and linking slots for distributing the result of the cell computation to other cells requiring that result as an operand. Circuitry is provided for utilizing tag bits to determine automatically when all operands required by a processor are available and for scheduling the primitive for execution in a queue. Each memory cell of the module may be associated with any of the primitives, and the particular primitive to be executed by the processor associated with the cell is identified by providing an index, such as the cell number for the primitive, to the primitive lookup table of starting addresses. The module thus serves to perform functions previously performed by a number of sections of data flow architectures andmore » coexists with conventional shared memory therein. A multiprocessing system including the module operates in a hybrid mode, wherein the same processing modules are used to perform some processing in a sequential mode, under immediate control of an operating system, while performing other processing in a data flow mode.« less

Inventors:
 [1];  [1]
  1. (Albuquerque, NM)
Issue Date:
Research Org.:
AT & T CORP
OSTI Identifier:
867242
Patent Number(s):
4893234
Assignee:
United States Department of Energy (Washington, DC) SNL
DOE Contract Number:  
AC04-76DP00789
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
multi-processor; including; data; flow; accelerator; module; computer; intelligent; memory; added; multiprocessor; arrangement; shared; tagged; architecture; assigns; locations; holding; values; correspondence; arcs; leading; node; dependency; graph; primitive; computation; associated; corresponding; cell; slots; operands; execute; identifying; pointer; linking; distributing; result; cells; requiring; operand; circuitry; provided; utilizing; tag; bits; determine; automatically; required; processor; available; scheduling; execution; queue; primitives; particular; executed; identified; providing; index; lookup; table; starting; addresses; serves; perform; functions; previously; performed; sections; architectures; coexists; conventional; therein; multiprocessing; operates; hybrid; mode; processing; modules; sequential; immediate; control; operating; performing; processing modules; accelerator module; data flow; memory cell; flow computer; data values; processing module; data value; /712/

Citation Formats

Davidson, George S., and Pierce, Paul E. Multi-processor including data flow accelerator module. United States: N. p., 1990. Web.
Davidson, George S., & Pierce, Paul E. Multi-processor including data flow accelerator module. United States.
Davidson, George S., and Pierce, Paul E. Mon . "Multi-processor including data flow accelerator module". United States. https://www.osti.gov/servlets/purl/867242.
@article{osti_867242,
title = {Multi-processor including data flow accelerator module},
author = {Davidson, George S. and Pierce, Paul E.},
abstractNote = {An accelerator module for a data flow computer includes an intelligent memory. The module is added to a multiprocessor arrangement and uses a shared tagged memory architecture in the data flow computer. The intelligent memory module assigns locations for holding data values in correspondence with arcs leading to a node in a data dependency graph. Each primitive computation is associated with a corresponding memory cell, including a number of slots for operands needed to execute a primitive computation, a primitive identifying pointer, and linking slots for distributing the result of the cell computation to other cells requiring that result as an operand. Circuitry is provided for utilizing tag bits to determine automatically when all operands required by a processor are available and for scheduling the primitive for execution in a queue. Each memory cell of the module may be associated with any of the primitives, and the particular primitive to be executed by the processor associated with the cell is identified by providing an index, such as the cell number for the primitive, to the primitive lookup table of starting addresses. The module thus serves to perform functions previously performed by a number of sections of data flow architectures and coexists with conventional shared memory therein. A multiprocessing system including the module operates in a hybrid mode, wherein the same processing modules are used to perform some processing in a sequential mode, under immediate control of an operating system, while performing other processing in a data flow mode.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1990},
month = {1}
}

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