Planarization of metal films for multilevel interconnects

Tuckerman, David B

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Title: Planarization of metal films for multilevel interconnects

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Abstract

In the fabrication of multilevel integrated circuits, each metal layer is anarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

Inventors:

Tuckerman, David B ^[1]

Livermore, CA

Issue Date:: 1989-01-01

Research Org.:: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

OSTI Identifier:: 866887

Patent Number(s):: 4814578

Assignee:: United States of America as represented by Department of Energy (Washington, DC)

Patent Classifications (CPCs):: H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

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H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
H01L21/268 - using electromagnetic radiation, e.g. laser radiation
H01L21/32115 - {Planarisation}
H01L21/7684 - {Smoothing
H01L21/76886 - {Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances}

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DOE Contract Number:: W-7405-ENG-48

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: planarization; metal; films; multilevel; interconnects; fabrication; integrated; circuits; layer; anarized; heating; momentarily; melt; melted; sweeping; laser; pulses; suitable; width; typically; microsecond; duration; increments; eliminates; irregular; discontinuous; conditions; successive; layers; method; particularly; applicable; ground; power; planes; allows; dielectric; planarized; produce; planar; interconnect; structure; useful; vlsi; wafer-scale; integration; metal films; multilevel interconnects; dielectric layers; metal film; dielectric layer; laser pulses; particularly applicable; metal layer; laser pulse; integrated circuits; integrated circuit; successive layers; suitable width; vlsi circuits; successive layer; sweeping laser; wafer-scale integration; power planes; planar multilevel; planarization method; multilevel integrated; multilevel interconnect; microsecond duration; momentarily melt; interconnect structure; eliminates irregular; layer eliminates; discontinuous conditions; /219/438/

Citation Formats


                    Tuckerman, David B. Planarization of metal films for multilevel interconnects.  United States: N. p., 1989. 
        Web.

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                    Tuckerman, David B. Planarization of metal films for multilevel interconnects.  United States.

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                    Tuckerman, David B. Sun .  
        "Planarization of metal films for multilevel interconnects".  United States.  https://www.osti.gov/servlets/purl/866887.

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@article{osti_866887,

  title        = {Planarization of metal films for multilevel interconnects},

  author       = {Tuckerman, David B},

  abstractNote = {In the fabrication of multilevel integrated circuits, each metal layer is anarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {1989},

  month        = {1}

}

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Planarization of metal films for multilevel interconnects by pulsed laser heating

Patent Tuckerman, David B [Livermore, CA]

In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scalemore » integration. « less
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In the fabrication of multilevel integrated circuits, each metal layer is anarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scalemore » integration. « less
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Planarization of metal films for multilevel interconnects

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In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scalemore » integration. « less
Planarization of metal films for multilevel interconnects

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In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping lase pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scalemore » integration. « less
Planarization of metal films for multilevel interconnects

Patent Tuckerman, D B

In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scalemore » integration. 6 figs. « less

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