Analog storage integrated circuit

Title: Analog storage integrated circuit

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Abstract

A high speed data storage array is defined utilizing a unique cell design for high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates between the signal input and a storage capacitor. The gates are controlled by a high speed row clock and low speed column clock so that the instantaneous analog value of the signal is only sampled and stored by each cell on coincidence of the two clocks.

Inventors:

Walker, J. T. ^[1]; Larsen, R. S. ^[2]; Shapiro, S. L. ^[1]

(Palo Alto, CA)
(Menlo Park, CA)

Issue Date:: 1989-01-01

Research Org.:: Stanford Linear Accelerator Center (SLAC), Menlo Park, CA

OSTI Identifier:: 866868

Patent Number(s):: 4811285

Assignee:: Board of Trustees of Leland Stanford Junior University (Stanford, CA) SLAC

DOE Contract Number:: AC03-76SF00515

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: analog; storage; integrated; circuit; speed; data; array; defined; utilizing; unique; cell; design; sampling; rapidly; changing; signal; input; gates; capacitor; controlled; row; clock; column; instantaneous; value; sampled; stored; coincidence; clocks; signal input; data storage; storage capacitor; integrated circuit; speed data; cell design; speed sampling; rapidly changing; /365/

Citation Formats


                    Walker, J. T., Larsen, R. S., and Shapiro, S. L. Analog storage integrated circuit.  United States: N. p., 1989. 
        Web.

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                    Walker, J. T., Larsen, R. S., & Shapiro, S. L. Analog storage integrated circuit.  United States.

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                    Walker, J. T., Larsen, R. S., and Shapiro, S. L. Sun .  
        "Analog storage integrated circuit".  United States.  https://www.osti.gov/servlets/purl/866868.

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@article{osti_866868,

  title        = {Analog storage integrated circuit},

  author       = {Walker, J. T. and Larsen, R. S. and Shapiro, S. L.},

  abstractNote = {A high speed data storage array is defined utilizing a unique cell design for high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates between the signal input and a storage capacitor. The gates are controlled by a high speed row clock and low speed column clock so that the instantaneous analog value of the signal is only sampled and stored by each cell on coincidence of the two clocks.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {1989},

  month        = {1}

}

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