Sputtered pin amorphous silicon semi-conductor device and method therefor

Moustakas, Theodore D; Friedman, Robert A

Title: Sputtered pin amorphous silicon semi-conductor device and method therefor

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Abstract

A high efficiency amorphous silicon PIN semi-conductor device is constructed by the sequential sputtering of N, I and P layers of amorphous silicon and at least one semi-transparent ohmic electrode. A method of construction produces a PIN device, exhibiting enhanced physical integrity and facilitates ease of construction in a singular vacuum system and vacuum pump down procedure.

Inventors:

Moustakas, Theodore D ^[1]; Friedman, Robert A ^[2]

Berkeley Heights, NJ
Milford, NJ

Issue Date:: 1983-11-22

Research Org.:: Solar Energy Research Institute

OSTI Identifier:: 864793

Patent Number(s):: 4417092

Application Number:: 06/243,754

Assignee:: Exxon Research and Engineering Co. (Florham Park, NJ)

Patent Classifications (CPCs):: H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02E - REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION

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H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
H01L31/03921 - {including only elements of Group IV of the Periodic System}
H01L31/075 - the potential barriers being only of the PIN type
H01L31/202 - {including only elements of Group IV of the Periodic System}

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02E - REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
Y02E10/548 - Amorphous silicon PV cells

Y - NEW / CROSS SECTIONAL TECHNOLOGIES Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE Y02P - CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
Y02P70/50 - Manufacturing or production processes characterised by the final manufactured product

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DOE Contract Number:: XZ-0-9219

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: sputtered; amorphous; silicon; semi-conductor; device; method; efficiency; constructed; sequential; sputtering; layers; semi-transparent; ohmic; electrode; construction; produces; exhibiting; enhanced; physical; integrity; facilitates; ease; singular; vacuum; pump; procedure; amorphous silicon; vacuum pump; semi-conductor device; semi-transparent ohmic; ohmic electrode; sequential sputtering; silicon semi-conductor; exhibiting enhanced; transparent ohmic; efficiency amorphous; /136/204/257/

Citation Formats


                    Moustakas, Theodore D, and Friedman, Robert A. Sputtered pin amorphous silicon semi-conductor device and method therefor.  United States: N. p., 1983. 
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                    Moustakas, Theodore D, & Friedman, Robert A. Sputtered pin amorphous silicon semi-conductor device and method therefor.  United States.

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                    Moustakas, Theodore D, and Friedman, Robert A. Tue .  
        "Sputtered pin amorphous silicon semi-conductor device and method therefor".  United States.  https://www.osti.gov/servlets/purl/864793.

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@article{osti_864793,

  title        = {Sputtered pin amorphous silicon semi-conductor device and method therefor},

  author       = {Moustakas, Theodore D and Friedman, Robert A},

  abstractNote = {A high efficiency amorphous silicon PIN semi-conductor device is constructed by the sequential sputtering of N, I and P layers of amorphous silicon and at least one semi-transparent ohmic electrode. A method of construction produces a PIN device, exhibiting enhanced physical integrity and facilitates ease of construction in a singular vacuum system and vacuum pump down procedure.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {1983},

  month        = {11}

}

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